RISC
  Reduced instruction set computer.
  Also called load/store architecture

  Some features of RISC already appearing in CPU designs in the 1960s and 70s.

  Formally developed in the 1980s.

  Contributing factors
    Memory becoming cheaper.

    Cost of manufacturing a CPU cheaper.

    The prevalence of C code helps to move programs to newer CPU designs 
      more easily.

  Newer design - tends not to have to deal backward compatibility
    (fewer older obsolete instructions or programming modes)
   
  RISC is NOT meant to imply the total number of instructions is fewer.
 
  Instructions designed to perform a single simpler (reduced) action.
    Uses multiple simple instructions to perform the same action as a CISC
      instruction.

  All instructions (opcode/operand) single standardized word size. 

  One or more complete instructions (opcode/operand) fetched in one memory 
    access.  Data bus width = size of or whole multiple of instruction size.

  Often big-endian.

  Many general purpose registers to hold and manipulate data once it is
    fetched into the CPU.

    Some designs use register files 
      grouped into duplicate sets.
 
      Each of these sets may be assigned to different process or subroutine.
   
      On some CPU designs, 
        these register sets overlap, allowing variables to be passed between 
        routines simply by adjusting the register window.

    Some designs use alternative register sets.
      Duplicate version of primary registers.
      Non-overlapping.
      Only one set active at any time.
      But simple command swaps active register set.
    
  High level language compilers take the burden of coding many software steps 
    off of the programmer.