Limited address types :

    Direct memory referenced by operand. 
      Direct memory references are usually limited in range.
    
    Register indirect
      Register holds address of memory being accessed. 
       (indirect pointer).

      Indirect important for larger address ranges.

      But require additional steps to initialize (load) register pointer.
      
  Only read/write (load/store) between memory and CPU. 
    Because read/write may not complete in 1 clock cycle,

      NOP padding or out of order coding may be used to improve performance.

    RISC CPUs expect to run on cached memory systems.

  Any/All computational activity occurs only between registers in CPU.

  Instructions decoded by hardwired decoder, very fast but unchangeable.
    Most RISC commands are too simple to make microcode necessary.

  Goal is to fetch, decode and execute instruction in one cycle.
    In practice, most RISC chips can do most work in 1 to 2 cycles.

    Although branch instructions may trigger a 'stall' to allow the CPU
      to update the PC and registers.
 
  Requires programmer/compiler to implement more complex actions 
    via software algorithm.

  Simple design allows :
    Faster clock cycles.
    Shorter data-paths.
    Fewer stages. 
    Fewer propagation delays.
    Wider paths easier to implement.
    Lower power consumption.

  Simple instruction design makes efficient pipe-lining easier.

  RISC pipeline
 
  Pipeline length : 5 stages. 

    Instruction fetch (whole instruction).
    Instruction decode
    Execute
      Register to Register, simple math completed by end of clock cycle.

      Memory reference - calculate target data's memory location.
        RISC generally supports 5 address modes.
          Direct 
          Indirect (pointer register)
          Indirect Indexed (pointer register and index register)
          Indirect displacement (pointer register and hard coded offset)
          Indirect dIndexed isplacement 
            (pointer register, index register, and hard coded offset)

      Multi-cycle, more complex instructions such as mul/div.
        Done in parallel with secondary registers, 
          allowing data path to be used for next instructions.

        May create data-dependency hazard.

    Memory access
      For an indirect memory read, calculating the memory address is 
        considered part of the execute stage.

      Accessing the memory is this stage.
      # remember calculations are never done during a memory access.

    Write-back - move results of previous actions to specified registers.