CISC CPU often supports microcode.
  
  On simpler CPUS, the opcodes' actions are stored in PLAs.
    And consist of only a couple of steps or 'stages'.

  On more advanced CISC CPUs, instructions are processed as multi-step 
    programs called microcode.
   
  Microcode CPUs have an 'interpreter' circuit for processing an instruction.

    Specific microcode instructions target specific logic circuits. 

    This allows various logic circuits to be accessed in varying order.

    Different instructions can access unused logic circuits at same time.

  On higher end CPUs, the sub-task implementations may be stored in 
    Flash memory or even high-speed RAM.

  Benefits 
    Easier to pipeline when instruction has a well defined set of discrete 
      steps.

      Current Pentiums treat instructions as sequences of simpler RISC 
        style instructions. 
        Modern (Intel i3, i5, i7) designs at 14 stages.

    Easier to detect hazards and work around them.

    Allows different instructions to use only logic required.

    Allows repair of instruction.

    Allows addition of newer instructions.

    Allows reprogramming of CPU (different set of instructions).
      More common in areas of research.

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Down side - CISC :

  Paradox
    While task runs at hardware level faster than software equivalent.
      Decoder more complex and slower, even for simple tasks.
      More gates to sequence through before final action achieved.

  Pipe-lining more difficult to implement especially if number of stages large. 
    May required buffers between stages - slowing throughput.

  Made it harder to design compilers because of the variability and 
    complexity of available instructions.
    Compiler often did not select best instruction.

  Additional issues
    Increased number of gates means increased power usage.