Control bus (packet)
  Control bus provides a variety of signals needed for proper interaction of 
    units.

  Common controls (specific controls vary by bus architecture).
    Clock - provides for synchronization of system.

    Data direction - specified the direction of data movement between master
      and slave. Bus itself is bidirectional but target logic often includes
      internal multiplexing to distinguish between input and output.

    Memory/IO - indicates whether address specified identifies primary
       memory or an I/O device.

    Bus arbitration (request/grant)- provides correct interaction on
      multi-master systems. Each device has dedicate pair.

    Interrupt - used by devices to request attention from master.

    Reset - causes the system to return to initial power up or start state.

    Control/Status - used between master/slave (initiator/target) units 
      to establish a task session and monitor/report status of task.

    Examples :

      Conventional PCI
      - 1992 (created) - 2003 (PCIe) - 2004 (last revision) - current but rare.

        32-bit address/data lines to transmit both address and data information.

        !FRAME to signal a frame of data consisting of mutliple 32-bit
          transfers.
          
          First transfer in frame is an address and command.

        4-bit command/byte enable (C/BE)
          During address transfer, represents a 4-bit command, 
            such as burst read, burst write, flush, etc.
             

Burst mode (alternatively burst-mode) is a generic electronics term referring to any situation in which a device is transmitting data repeatedly without going through all the steps required to transmit each piece of data in a separate transaction.

   From  en.wikipedia.org/wiki/Burst_mode_(computing)


          During subsequent data transfers, functions as a mask applied to
            the 32-bit (4 byte) data bus.

        PCI performs burst transactions. An initiator initiates a transaction 
          session with a target using !FRAME, C/BE, and data lines. 
 
        Buffers set up on initiator and target.

        Initial command and addressing information sent over C/BE 
          and data lines.

        Multiple 32-bit words of data may then be burst transmitted with 
          minimal additional overhead.

        The C/BE allows the transfer of less than 4 bytes at a time.

        There is no protocol limit to the size of the data burst transfer.
           But there are practical limits.


        Transaction is unidirectional but may be moved in either way.

        Under normal circumstances, only one initiator/target transaction can
          occur on the PCI bus at a time.

        PCI's efficiency improves as the size of transaction increases. 
          i.e file access on a hard drive.

        Very small transactions occur very high overhead. 

        Under certain circumstances a transaction can be suspended and 
          another initiator can start a different transaction.   

        GNT/REQ - arbitration lines. For selecting an initiator.
          Each connector has its own GNT/REQ lines.
                
        INT#  - four interrupts lines available to any device.
          Each connector has all 4 interrupt lines. Lines are shifted on
            each connector. A device may use all 4 interrupts.
            
        IDSEL - before a PCI device can be seen by the system, the PCI 
          controller must configure the interface. Each interface has its
          own IDSEL line that is used by the controller to target specific
          device/slot.

        DEVSEL - used by selected target to ackknowledge recognition of its
          selection. Must respond within 3 clock cycles.

        IRDY/TRDY - ready status lines for initiator and target. 
          Used when buffers full/empty to provide short pauses in transfer.
         
        STOP - a type of abort request.

       # not complete list, bus includes error or special purpose signals.
        

General Purpose Interface Bus
        The GPIB is a true asynchronous bus. All data movement is controlled
          by a series of control/status signals.

        8-bit data bus used for address/data transfers.
          Single-ended signalling.

        8-bit ground lines.

        8 Control/status signals pull-up or pull-down.
          This means that all devices have to respond to signal.

          EOI - end or identity (marks the end of the data stream). 
          DAV - Data valid
          NRFD - Not ready for data
          NDAC - Not data accepted (Data not read)
          IFC - Interface clear (reset)
          ATN - Attention (data represents a command )
          SRQ - service request (interrupt) - requires polling.
          REN - Remote enabled - used to transfer initiatior task.

          Control/Status line can be combined in a number of ways to indicate
            different tasks or statuses.

          These may be defined by a particular implementation of the bus.

        Devices are assigned a 5-bit ID (usually jumpers).

        Transfer initialization
          A device is chosen by the user as an initiator.

          A talker is selected by an initiator.
            (This arbitration requires human interaction)

            This consists of setting the device ID as data 
              and using the control/status lines to signal this.

            Selected talker responds with certain signals 
              as it becomes active.
         
          Talk selects a listner by similar procedure.
 
        
Begin data transmission.

  Talker indicates data invalid (new transaction) by bring DAV high.

  Listeners see DAV and finish last transaction. Each listener then brings 
    both !NRFD and !NDAC low indicating everyone in an idle state.

  Talker puts data on data lines. 

  Note that there is an implied time frame, after listeners have held
    both !NRFD and !NDAC low for a short time, each will allow !NRFD high.

  When Talker sees that all devices are listening, it indicates that 
    new data is valid by taking !DAV low.

  As each listener reads data, it indicates that it is busy processing the new 
    data by bringing !NRFD low. 

  Once read, each listener then indicates it has taken the new data it allows
    !NDAC to go high.

    Only addressed device will process it further and slowest device determines
    overall speed.
 
When all listeners indicate data accepted, talker indicates data invalid and 
  process starts over for next byte of data. (!DAV high)

# Note that by definition of burst above, GPIB does support burst mode. The
selection of talker and listener is selected and then multiple bytes of data
may be transferred with out having to reselect devices.

          
   Misc - others as appropriate to specific bus architecture.