Bus synchronization.
  Synchronous bus 
    Clock is provided to signal boundaries of state changes.

      Can be dedicated clock signal

      Can be embedded in data stream, using techniques like NRZI, RLL, and/or 
        Manchester encoding.
 
    Simplifies control and interaction between devices.

    But requires more expensive and precise controls.
      And/or encoding/decoding of clock within bit stream.

    Requires that devices function in a defined parameters.
      received data must be latched within defined clock periods.

      May not act in a single clock cycle, but information must be ready at 
        specific change of clock cycle.

      Or additional buffer circuitry added to isolate the asynchronous portion.

    Modern system bus implementation often uses a tiered design to allow 
      buffering and bus segments that function at optimal timing for a set 
      of devices or interfaces.


  Asynchronous bus
    Data/signal may arrive at any time.

    Additional control signals needed to guarantee proper interaction.
      Handshaking.  (Review the timing diagram of RAM)

    Devices interact only when and if necessary.

    Small packets of data may be encapsulated in Start/Stop bit patterns.

    Or require additional signals/lines to indicate when bit/byte is 
      valid and usable.

    Most implementations use local clocks at approx. same frequency
      to make reasonable measurements of bit stream.

    Truly asynchronous bus may have no clock info at all
      Uses extensive hand-shaking and control lines.

Real vs. Virtual bus implementation.
    Real - bus has dedicated lines for address, data, control, and power.

    Real shared - some implementation use data lines for transmitting 
      address and data on alternate clock cycles or transmission periods
      or at alternative levels of the clock cycle.

    Virtual - with the development of networking and packet driven 
      communications, it is practical to use a limited number of lines to
      deliver address, data, and control information by encoding it on an
      appropriately identified packet. 

      Packet may be flagged to ID the 'type' of information being transmitted.
        e.g SATA, PCIe, USB, Ethernet