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Lecture 
Synchronous Dynamic Ram (SDRAM)

From the introduction of SDRAM on wikipedia

Previous to SDRAM, DRAM access and timing was handled by a memory controller 
circuit that ran asynchronously (independent) to the system or bus clock 
and would put the CPU in a suspended state while addressing/accessing memory.


SDRAM uses a split memory controller model. In modern systems, part of the 
controller resides on the CPU chip itself.

And part of the control resides on the memory chips. The chips incorporate
a command interpreter.



Appaloosa [CC BY-SA 3.0 (http://creativecommons.org/licenses/by-sa/3.0/)]

The CPU controller uses the RAS, CAS, WE, BA(bank access) and address lines 
to issue commands and memory addresses to the command interpreter on the
memory chips.

The interpreter then executes the memory access and handles the actual row
and column stobing internally.

The interaction between the two sides of the controller is done on a clocked,
synchronized bus. This bus is often independent of other buses on the system. 

Particular memory modules(models) will use a specific number of clocks from the
time a memory access is initialized and when the first actual access occurs.

After memory access can occur on each up clock tick for a limited burst.

DDR allows data transfers on both the up and down tick.

Early versions of SDRAM actually slower than other RAMS except in burst
mode (multiple sequential memory accesses).

An important aspect of SDRAM is that it works well with modern CPU cache 
which often requires multiple sequential bytes of memory to fill a cache line. 

This can be accomplished with a single read command to SDRAM. And a cache 
line can quickly be filled with SDRAM burst reads.


Worth reading : 

  https://alchitry.com/blogs/tutorials/sdram-verilog
    This one gives a program a controller might run, so you see how the
      ordering of the step and signal access. 

  https://taututorial.yolasite.com/

  https://www.anandtech.com/show/3851/everything-you-always-wanted-to-know-about-sdram-memory-but-were-afraid-to-ask
  * This one is rather technical

  https://www.realworldtech.com/sdram-bank-interleaving/

SDRAM - synchronous DRAM.
  SDRAM still accessed via an external memory controller that provides row
    and column split addressing but controller delivers commands and addressing
    based on a predefined timing synced with the bus clock.

  Additional advanced memory controller circuitry is incorporated into to the 
    RAM chips which interprets control signals differently than historic DRAM
    when issued on the command cycle.

    RAS, CAS, CS, WE, BA (Bank access), A10 and Ax address lines are 
      multiplexed. On initial access to a memory module, they are used by 
      the controller to issue commands to the memory module. 

      Once the module is 'programmed', they then are used to specify addresses
        being accessed.
 
    The controller is able queue multiple requests. 

    The controller is capable of rearranging requests for optimal memory
      access on a row.

    When a memory row accessed, it is written into a buffer which is also
      used to refresh that row at that time.
 
   
   How the read occurs at the transistor level.
   
    Sense amp disconnected.

    Bit lines are precharged to voltage midpoint between 0 and 1.
      Bit lines have capacitance and will hold this for a short time.
    
    Precharge is switched off.

    Target row-line select is driven high causing all bits of that row to 
      either charge or discharge onto their bit lines based in their individual 
      setting. 

    Sense amp is turned on to detect this.
    
    The target bit is put on the data bus.

    The contents of the sense amp are written back to the accessed row.

    Write is similar except the bit from the data bus is written to sense amp
      before the refresh write is performed.

    Because scheduled refreshes occur independent of read/write, if a refresh
      is already in progress, then the read/write must wait.

    Scheduled refreshes perform the same except data is not transfered in/out
      of the row.


    A common design might be 4 x ( 8192 1-bit memory bit rows ) (SDRAM)
      x 8 chips that make up a byte.  (SDRAM)
        This adds up to a 32 bit (4 byte) wide memory access.

      DDR doubles this.
        This allows an access of 64 bits or 8 bytes for a single memory access.

    Additionally, SDRAM modules designed to perform up to 8 successive reads 
      or writes to the buffer before the row has to be closed so the buffer
      can be used to perform other row refreshes.

    SDRAM designs support from 2 to 8 banks. Each bank has its own buffer
      and can be processed independent (parallel) to other banks.

      Only one bank is read or written 
        but other banks can be refreshed, closed, or open for subsequent read. 

      Successive 8 byte sequence of memory can be interleaved between banks.
        This allows a just accessed row to refresh while the next 8 bytes
        is read/written on the alternative bank.

    It still takes several cycles to perform an initial read/write.

    But the combination of advanced logic, large row latching, and multiple
      banks allows memory to often complete several memory accesses on each
      subsequent clock after initial setup.

  SDRAMS are usually mounted on a DIMM, Dual in-line memory Module which 
    provides 8 byte wide data I/O.

  Burst reads can be programmed to read the bytes in any order as long as 
    they are from the same row (page).
    
    Burst length 1-8 word.  Memory 'word' is determined by the width of the 
      data bus - current design 8 byte (64 bit).
        (Google sdram burst length)

    The sequencing of the 8 word ordering access as some flexibility.
    
  Rows in other banks can be prep'd while current row being accessed.   

  

Improvements in throughput of SDRAM come with upping system clock, widening
  the bus interface, banking memory arrays internally, and accessing chip on 
  both up and down tick of system clock (DDR). 

  SDRAM 66MHz, 100MHz, 133MHz, 150MHz, 3.3 V.
     168 pin  * variations such as SO-DIMM differ.
  
  Source
  
  Source

  DDR - double data-rate SDRAM
    Uses double pumpingng to double the throughput of actual data transfers.

  DDR2, DDR3, DDR4 are generations.
    DIMMs are slotted differently to physically prevent use of wrong type.
    Speed differences may mix but not type.

    DDR access on both up/down tick of clock, 64 bit wide data bus, 100-200MHz 
      front side bus (FSB). Toggles between internal banks at each access.  
      2.5V, 184 pin.

  DDR2 (2 generation) - 200-553 MHz FSB, 4 internal accesses per clock. 64 bit
    wide data bus. 
    2 Access per clock but supports faster external clock.
    Could burst 4 reads before refresh - 8 bytes wide by 4 reads.
    1.25 V, 200 pin.

  DDR3 - 400-1066 MHz FSB, 8 internal accesses per clock. 64 bit wide data bus.
    Could burst 8 reads before refresh - 8 bytes wide by 8 reads.
    1.5 or 1.65 V, 240-pin DIM.

  DDR4 - 800-1600 MHz. Released to market 2014. 
    Lower voltage, 1.2 V., 1.05 V. being anticipated. 
    16 internal banks.
    Parity check on command/address bus.
    CRC on data bus.
    288-pin DIM.
 
  DDR5 - March 2017 JEDEC announced standard under development.
    Plans for double bandwidth of DDR4

  Each update design lowered running voltage levels to save power. 
  Each design needs its own controller on mother board, not cross-compatible.

  * Modules of different speed can be mixed in a system but must be of type
    designed for system (all DDR or all DDR2). But system will run at slowest
    component.

  * Modules are keyed so to prevent using wrong type.

  * CAS latency - commonly specified in system CMOS but some SDRAM chips
    can be queried for that information. Some systems expect this, others
    don't.

*****************

Register (buffered) SDRAM - on systems supporting memory > 8GiB (servers) 
  address and memory control signal cannot drive all SIMs. Registers are 
  added to latch and boost signals in each SIM. Add 1 clock cycle to access.

ECC SDRAM - uses SECDED Hamming code (8 additional bits to check 64 + a parity
  bit), can catch and correct 1 bad bit and catch 2 bad bits. Used in servers,
  especially for banking.

  Register and ECC are independent of each other but are often found together.

  Both add to cost and may slow access speed some.

*****************

Other RAM types.

Check out : https://whatis.techtarget.com/reference/Fast-Guide-to-RAM

Ram-bus - better burst access than early SDRAM but slower at singular reads, 
  more expensive, and more power hungry. Proprietary, part of cost was 
  licensing. ~1999 - 2003  DDR SDRAM much faster.

  Rambus was common in game machines where large blocks of pre-configured
  memory (e.g particular game scene) are transferred to video memory.

  SLDRAM - an open alternative to Ram-bus, used in Sony and PlayStation 3, very
  high throughput per pin, useful in systems where a narrow data bus is desired.

XDR RAM - Ram-bus' redesign of the original Ram-bus. 

VRAM - video ram provide a second port to allow video chip to directly access
memory. Both ports can be accessed at the same time. 

PCM, PRAM - phase change memory. Uses same material types as re-writable DVDs,
  but measures resistance rather than reflectively. No refresh.

FeRAM - ferroelectric.  'magnetic core' memory at a microscopic level. Still
larger than flash memory. Reads destructive. But doesn't need refresh.

MRAM - magnetoresistive RAM - another 'magnetic core' memory. But, reads not
destructive. No refresh. Writes require more power. 

https://www.eeherald.com/section/design-guide/FRAM-MRAM-PRAM-nonvolatile-flash-replacement-memories.html