CPU instruction design issues.

Instruction design is affected by a variety of issues.

Type of data being manipulated and granularity (size of data units)
  Recognized units

  Bit - single memory cells.
    Target usually dedicated purpose bits in status register or other logic.
    Often accessed by dedicated machine instructions. SEC - set carry, etc. 

  Boolean - applied to bytes/words in registers or memory.
    Logical AND, OR, XOR  (Masking)

    Affects flags differently than math. 
      Zero and Sign, but not Carry or Overflow

  Nibble - 4-bit, accessed via masking, where instruction operand specifies 
    which bits to work on. Some instructions may have half byte modes for
    register manipulation commands. Also BCD style instructions.

  BCD - custom instructions to work with binary coded decimal and use
    alternative flags in CPU.
    Example : IBM 360 Pack instructions 

  Byte - generally smallest working unit directly addressable by instruction.

  Word - 16, 32, or 64 byte manipulation.

  String - consecutive series of storage locations.
    Examples : 
      IBM 360 Pack instructions.
      Intel loop instructions.

  Integer - 16-bit, 32-bit, 64-bit sizes. Slightly different instructions
    for each, so overflow/sign handled correctly.  

  Float - IEEE standard 
    Separate instructions and registers. 
    Often separate processor core on chip.

  Addresses - direct and pointers.
    Valid ranges
      IBM 360 
        GPRs 32 bits when viewed as data..
        R0 treated as null if used as address. 
        BC mode recognizes only 24 bit-address
        EC mode recognizes only 31 bit-address

      ARM 
        32-bit indirect (register held) address. 4 GiB address range.
        23-bit signed Word(4-byte) aligned offset (operand)
          Giving +/- address range.
          Note that 

      Intel x86
        uses segment registers combined with
          Instruction pointer
          Stack Pointer
          Base pointer
          and possibly index register so arrive at a target address.
 
    Custom instructions to address alternative buses.
      Intel x86
         IN and OUT that address CPU port interace pins rather than
         memory address/data pins.
      IBM 360
        channel instructions 

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