CPU instruction design issues.

Instruction design is affected by a variety of issues.

Size of instruction and operands.
  Variation in size and number of operands requires opcode to indicate 
    if additional fetches needed to obtain full instruction.

  RISC limits instruction to single standard size.
    Fetch is single action.
    Not required to use all bits of instruction word.

Addressing mode
  Variety - different types of addressing (effective addressing).

  Orthogonality - addressing mode independent of register used or function.
    If you have 16 work registers - a particular addressing mode can use 
      any register (or combination of). Requires additional bits in opcode.

Complexity of instruction.
  Instruction may performs complex task and use compound addressing (CISC)
    Denser code - more efficient use of memory.
    Performance improvement on complex tasks.

  Instruction performs single simple task (RISC)
    Memory interaction limited to Fetch/store.
    Limited addressing modes, simpler logic, cheaper CPU
    Simpler, more efficient pipeline.
    Hard wireed decoder much faster.
    Improved performance on simple tasks.

How data is stored/processed inside the CPU (work registers).
  General Purpose registers - quantity.
    Limited Accumulator type vs. Register Files

  Dedicated purpose registers - assigned specific tasks.

  Stack style Operands found on top of memory stack.

  Early CPUs designed wiht limited number of CPUs.
    File registers used on new CPUs requiring legacy compatibility.

  Modern CPUs designs start with large number of GPRs.

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