Standard PCI is multi-port bus.
    Multiple devices introduce noise (and power drain) to the system.
    By going p to p, cleaner data transfer.
      Enough power to talk to all devices.

    Multi-port bus requires advanced arbitration and addressing.
    By going p to p, fewer lines, lower overhead.
      Arbitration still occurring on controller chip. 

    Transaction driven.  
      Arbiter selects an initiator (bus master).
      Initiator addresses a target.  
      Data is transferred unidirectionally during a transaction.

    Each transaction/task with particular device must be completed or
      stopped before another can be imitated.
        Sender signals data transmission completed.
        Receiver signals buffer full.
        Sender signals stop/pause because need to access more data.
        Either may signal error. 

    PCI 2 does allow for suspended transaction. 
      But device must request and wait for arbitration to resume.

  Serial yields simpler design, therefore lower latency and propagation 
    delays and no skew.

    Packet based protocol.

    Asynchronous - time independent - printer, keyboard.
       Data integrity essential. Retransmission of data not recoverable.
     Tends to be small blocks.

    Synchronous - transmission predictable.
      Data integrity essential. Retransmission of data not recoverable.
      Large blocks and allows suspended transmission.
      Also, allows for packets between different initiators tnd argets 
        to be buffered and interleaved at switch/controller.  

    Isochronous - time sensitive streaming - video capture or transmission. 
      Invalid data discarded. Next block of data transmitted on time. 
  
    Supports hot plug-gable, hot swappable.
      Physical connectors designed to connect grounds before data. 

    Controller functions as switch with independent interfaces to each device.
      Allowing non-conflicing device pairing and packet interleaving.

    Address, data, and control packets both transferred over same lane.

  Modeled after Ethernet.
    Has a physical, data-link, and transaction layer.
      0.8V signal and differential measurements.
      2.5 G-baud signal per lane.
      8b/10b encoding for clock.

      CRC at data-link with handshaking to resend corrupted packets. 

      Transaction layer allows packets assigned to different tasks to be 
        interleaved.

      Separate lanes for each direction transfer in opposite direction 
        at same time.

      Requires clients to be with-in 16 inches of controller.

  
  Transfers vs. bits

  Bits/bytes - data being transferred.

  Transfers - actual bits generated and detected.

  Because of 8b/10b encoding (clock inclusion).
    Actual number of bits greater than bits needed to represent data

  8b/10b data rate 80% of transfer rate.

  128b/130 data rate ~98% of transfer rate.
  
 
  PCI-E 1.1  -  Clock speed 2.5 GHz.  2.5 GT/s / lane
    250 MB/s (x1 lane x1 direction) up to 8 GB/s (x16 x2) 
    However, estimate includes control and handshaking which is not data.      

    
x8 comparable to fastest AGP
    
2x faster than standard hard drive.

    Also, smaller data transfers less efficient.
      More overhead per byte of data and multi-lane not useful.

  PCI-E 2.0  -  Clock speed 5 GHz.   5 GT/s / lane
    16 GB/s  (x16 x2)
    500 MB/s / lane / direction 

  PCI-E 3.0 
    Clock speed 8 GHz.  8 GT/s / lane
    1 GB/s / lane  
    Uses 128b/130b  reducing overhead by ~20% 
    Requires clients to be even closer than PCI-e 2.
    8 GT/s transfer possible using all lanes.

  PCI-e 4  - in development 16GT/s

  External PCI-E - exists in limited form. But Hub and PtoP structure limits
    usefulness.

*******

 CPU -> North Bridge -> PCI-E -> SATA 

   or

 CPU -> PCI-E -> SATA