Data transmission modeled after network protocols.
PCI-e is treated as a tree network topology, with the controller (root
complex) at the base and nodes or switches that branch off.
* Application on system or device being accessed.
* Device core - PCI controller or device's PCI Interface.
* PCI-e layers
Transaction
Data Link
Physical.
Physical Layer
Normally the physical interface between mother-board and card.
But can be a cable or fiber optic.
Data link layer - delivery of individual Transaction Layer Packet (TLP)
This layer deals with delivering a packet correctly between nodes on
PCIe connection.
Data sent as packets encoded on RLL (8/10b or 128/130b) provided timing.
Packet holds/transmits address, data, or control info including interrupt.
Packet includes sequence number (unique id), especially useful for
multi-lane transmission.
Packet contains error correcting code.
Uses handshaking to acknowledge successful transmission of each packet.
Packet size : 64 bytes (Intel desktop), 128, 256, 512 1024, 2048, 4096
possible. If controller supports, it will confirm size with client
device. Settable in bios(?).
Packets can be striped across lanes if multiple lanes available.
Uses sequential numbering so skewing easily handled.
Failure to transmit data is a PCIe failure not data transfer failure,
failure not communicated to applications requesting task.
Transaction layer
Check out : https://www.fpga4fun.com/PCI-Express.html
https://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-1
Contents of packet.
Header : 3 or 4 Double-Words (32-bit)
Used to indicate type of transaction and size.
Payload : 0-1023 Double-Words
| STP | Sequence Number | Header | Data | Digest | CRC | End |