Variety of addressing modes - some very complex.
  Combined registers, register and or memory as pointers, indexed.

Variable number of operands - requiring multiple memory accesses.
  From none to 3 or more.

Instruction/operand - generally not tightly bound to data bus size.
  May support multiple data sizes: 8, 16, 32, and larger
  IBM 360 pack cmds include a length parameter.

Simplifies programming.
 
Task performed by single CISC instruction may run faster than same task 
  performed by sequence of simple RISC instruction steps.

As CISC CPU become more and more complex 
  Processing of each instruction slower (in clock cycles).
    More to decode and more circuits to select from.

CISC cpu instruction sets make techniques like pipelining more difficult.  

CISC CPU often supports microprogramming
  - instructions treated as little programs and dynamically interpreted
    at execution time - slower but more flexible.

  The decoder circuit is actually reprogrammable.
    Allowing repair of instruction.

    Allowing addition of newer instructions.

    Allowing reprogramming of cpu (different set of instructions).