CISC - complex instruction set computer
  Although advanced languages made coding easier,
    memory still very expensive,
    higher level languages run slower.

  Push to do as much work on the CPU hardware as possible with as few 
    instructions as possible (code density),
    as fast as possible.
 
  Individual machine level instructions evolved
    to do more related steps,
    and offer more flexible addressiing modes. 
      Pointers, pointers with offsets, lists of pointers, etc.
  
  Address orthogonality - addressing modes independent of instruction function.
    Address modes available to most instructions.

  Instruction/operand length - not tightly bound to data bus size.
    May have 0, 1, 2, or more operands.
      Decoder may perform additional fetches to obtain all information needed
        to execute instruction only when needed.

  Register use - non-orthogonal. 
    Early CPU designs - registers are a type of memory.
    Small number of registers. 
    Registers assigned specific tasks.

    Tends to favor fewer registers 
      (expense of actual registers and overhead of tracking). 

    Number of registers very greatly between data-path designs.
      6502 - 1 accumulator, 2 index registers.

      8088 - 4 mixed purpose, 4 Index/operand address registers.
        Primary function of the 4 'general' purpose 80x86 registers.
        A - accumulator.
        B - base
        C - counter.
        D - uses with a for math.

        Upgrade implemented by widened the same registers.

      IBM 360 - 16 GPR, 4 double floating point registers. $$$
        Precursor to RISC architecture. 

  Original design 
    Backwards compatibility - because so many hours invested in existing
      code, system purchasers wanted same architecture as previous system..
  
  Examples of instruction complexity :

    Single instruction performs complex or compound instructions.

      808x: LOOPNZ target-location 
        Decrement CX register, test CX and Z condition code flag. 
        If both CX != 0 and z flag is not set, 
          branch to loop-back (change contents of PC). 
        * Decrementing CX to zero does NOT affect the z flag.
        * takes 5/6 clock cycles.

        IDIV - integer divide, can use indirect addressing.

      IBM 360: ZAP D1(L1,B1),D2(L2,B2) 
        Zero a block of memory starting at address specified in register B1 
          plus the displacement value D1 for the length of L1.

        Then copy the packed number of length specified in L2 from the memory 
          block pointed to by the register B2 plus the displacement D2.

        Set appropriate condition flags.
         (This is a loop with a pair of internal counters).

      IBM 360 predates CISC/RISC concept but has both CICS and RISC features.
        RISC
          Large number of GPRs.
          Support large number of register to register commands.
          Limited addressing modes - although modes may be complex.

        CISC
          Very complex instructions available. 
          Variable length instructions.
          Compound addressing modes.
                L R1, 23(R2,R3)
          Single instruction performs memory data fetch 
            and specified calculation.