Z8

Zilog eZ8 - (current design). 
 16 bit, big-endian.

(google ez8 CPU manual)

Micro-controller has CPU, memory, and I/O interface all on same chip.
  Often preprogrammed at factory for specific task. Computer on a chip.

Could be used to control a microwave oven, automobiles dashboard, or 
  electronic fuel system, etc. 

Supports pipe-lining.

Fetch unit separate from Execution unit.
  Program counter (fetch) has own ALU for incrementing and branch/subroutine
    adjustment.
  
Harvard style access to memory.
  Code memory
    4 KiB internal ROM - Pre-programmed.  
    64 KiB K external ROM/RAM
     may be used to hold data.

  Data only memory
    ~64 K external RAM
  
Uses assembly code inherited from the Z80 (1975).
  
Z8 Register file - on-board sram memory module containing a large number of 
    registers.

    4K of register space depending on model.)

    @FFF - Stack pointer LB [7:0]
    @FFE - Stack pointer HB [3:0] (4-bit)
      Stack implemented in register space. 
      Pointer capable of using whole register space.

      Stack can be implemented in register space
      Or in external memory.

    @FFD - Register Pointer (RP)
      # acts as a pair of decoders.

      Register space segmented into 16 256-byte pages 
      and Working register groups 16 16-byte register groups.
      RP[3:0] - points to current working Page
      RP[7:4] - points to current register group.

      This allows the CPU to use classic z80 instruction sets.
        A task is assigned to a particular 16-byte register group 
        and multiple tasks may reside in the register file 
        although only one will be active at any time.

      # CPU supports extended addressing which allows access to 
        register memory outside of current working page and register group.
 
    @FFC - Flags
      C - carry [7]
      Z - zero [6]
      S - sign [5]
      V - overflow [4]
      
      The jump instruction itself has a 4-bit field recognizes 16 possible
        combinations of the CZSV flags. 

      D - decimal adjust [3] 
      H - half (BCD decimal carry) [2]
        D,H not testable by conditional jump cmds.

      F1[0], F2[1] - user flags, not testable by conditional jump.
         Most likely testable via masked test instructions

    @FFB-004 - General purpose registers usable by all instructions.
 
    @003 - Port 3 interface.
    @002 - Port 2 interface.
    @001 - Port 1 interface.
    @000 - Port 0 interface.

    
    Interrupt Mask Register

    Interrupt Request Register

    Interrupt Priority Register

    4 I/O Port usage : 

      Ports mapped to 1st 4 memory locations of register file.

      Port 0 - 2-nibble sized (4 bit) bidirectional i/o ports.
        Or 8 bit upper address byte of memory address register.

      Port 1 - can be used as a byte wide i/o port with pins from 
        Port 3 for handshaking.  Handshaking used when predictable 
        timing not available.

        Or as a multiplexed address/data port for addressing up 64K of 
        external memory.
          Port 0/1 used as a 16-bit MAR when accessing external memory.
            and Port 1 used as an 8-bit MDR. 

      Port 2 - bit programmable bi-directional.

      Port 3 - 4-bit input/4 bit output 
        Or hand-shaking and interrupt when used with other ports.
          (control/status lines)

      # Pair of timers with scalar parameters.
      T0 Prescalar
      Timer/counter 0
      T1 Prescalar
      Timer/counter 1

      Serial I/O

Fetch stage semi-independent of execute stage.
  Fetch stage fetches opcode and determines length of instruction.

  Fetches rest of instruction and adjusts program counter.

  Passed instruction to decode in execution stage 
    and starts processing next instruction.

  Except for brk, minimum 2 clock cycles for instruction execution.

Harvard Architecture (Modified?) - Two address spaces.
  Separate program memory. 

    Program memory on chip 

      1st 4K either permanent on-board ROM or flash and 60K of external ROM.
      (Externally programmed).

      Or up to 64K of r/w memory.

    1st 20 bytes of memory reserved for various system vectors (pointers). 
      Can point to external ROM containing interrupt codes.
 
    Addressable by the program counter performing opcode, operand fetches, or
      program branching.

    Addressable by specific instructions, LDC - load data constant.

  Data memory 
    Up to 64K of externally addressable memory with instructions that use
      port 0 and 1 to access external data memory. 
      This is separate from the program memory.

    Program counter cannot address this so it cannot contain code.  

    Only load, store allowed on data in memory. (RISC style)
      Data manipulation (add, shift, etc) done on data loaded into CPU 
      registers.
    
Z8