MOS 6502 family.
6502 diagram

1975 - Original release at 1/6 the price of competing CPUs.

3510 transistors. (later variations up'd this some).
WDC 65c02 - 11,500 transistors (remember CMOS doubles transistor count)


Source : https://en.wikipedia.org/wiki/MOS_Technology_6502

Apple II/IIe, Atari 2600, Nintendo, Commodore 64 and several other models.
1 MHz (later Apple 2GS with a 2 MHz CPU)
Original 6502 did not support pipe-lining. 6509, 6510 did.

8 bit, little-endian

6502 Registers
  16-bit program counter.
  16-bit  memory address register (address bus).
    Tri-state - CPU could be decoupled from address bus.
  64K bytes.
    (6509) uses memory locations 0 and 1 as decoders to provide
      16 banks of 64K or 1Meg of memory.
        Lower 4 bits of @ 0 pointed to bank of executing program code.

        Lower 4 bits of @ 1 pointed to bank of indirect addressed data.
          Allowed program to access memory in different bank.

        When $0 or $1 addressed, CPU rerouted the data to CPU pins P0-P3
          which in turn, connected to a 4-16 decoder
          which select 1 of 16 memory banks.

    (6510) uses memory locations 0 and 1 as control/data i/o port.
       Alternative plug-in CPU or Game BIOS and OS.

       @ 0 - data direction control for i/o port (@1) - bit programmable.
       @ 1 - internal input/output port register.  Direction could be mixed.
         These interfaced with the I/O pins P0-P7 of the CPU.
         Could be used as bank select (decoder), not as flexible as the 6509.

       56 instruction types with various addressing modes ( ~152 total ).
         CPUs from 2ndary sources sometimes had additional instructions.

       Uses Pipe-lining.

  8-bit Memory data register (data bus)

  8-bit Stack pointer (hard wired to a specific 256 byte block).
     Limited stack size and finite location made multi-tasking difficult.

  8-bit Instruction op-code register.
    Uses PLA to decode - very fast interpretation of op-code.
    Instructions 1-3 bytes.

  8-bit General purpose register called the accumulator.

  2 8-bit Index registers called x and y.
    Each could be used differently for different addressing modes.

    Used and zero page memory indirect addressing.
      Allowed code to use 1st 256 bytes of memory as external general
      purpose registers.

      Example :
      Memory location pairs 40/41, 42/43, 44,45 each contain a 16-bit value
        pointing to a block of memory where a table of values to be worked
        on reside.
        it.
LDY #0
LDA (40),y
ADC (42),y
STA (44),y


  8-bit condition code register.
    Conditions
      (N) Sign flag
      (Z) Zero flag
      (C) Carry flag - unsigned math.
      (V) Overflow - result of signed action carried or borrowed.

      (B) BRK command - flags whether a break instruction, op-code 00, or
        and IRQ encountered. Rarely of practical use.

    Control
      (I) IRQ Disable - mask to "ignore" certain interrupts.
        Set when already handling an interrupt.
        Or when changing @ 0 or 1 (6509).

      (D) Decimal mode - cause instructions to perform BCD.
        Modifies the interpretation of the sign and carry flags.

  Internal registers (non-user).