Data transmission modeled after network protocols.
PCI-e is treated as a tree network topology, with the controller (root
complex) at the base and nodes or switches that branch off.
Application layer
Application performs a system read/write call.
OS addresses mapped memory port.
PCI controller acts as the address decoder, latching the target address
and data.
* PCI-e layers
Software layer - driver/controller performing a transaction request.
Remember, actual target addressed with standard PCI protocol,
bus, device, function.
Transaction - generates Transaction Layer Packet (TLP)
Header, Data being transmitted, Error check.
Handles handshaking between sender and receiver.
Physical - serialization and transmission.
Serializes packet.
Encodes bytes in appropriate RLL symbols.
Creates differential signals on lanes.
Distributes across available lanes.
Data link layer - delivery of individual Transaction Layer Packet (TLP)
Encapsulates TLP, adds sequence ID, and additional error check.
This layer deals with delivering a packet correctly between nodes on
PCIe connection.
Data link layer uses ACK/NAK handshaking to acknowledge success of
transmission of each packet.
Transmitting node has a Replay buffer for repeating current packet
if NAK returned.
Packet size : 64 bytes (Intel desktop), 128, 256, 512 1024, 2048, 4096
possible. If controller supports, it will confirm size with client
device. Settable in BIOS(?).
Failure to transmit data is a PCIe failure not data transfer failure,
failure not communicated to applications requesting task.
Transaction layer
Check out : http://www.fpga4fun.com/PCI-Express.html
http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-1
Contents of packet.
Header : 3 or 4 Double-Words (32-bit)
Used to indicate type of transaction and size.
Payload : 0-1023 Double-Words
| STP | Sequence Number | Header | Data | Digest | CRC | End |