Interesting paradox.
  Parallel vs Serial buses.

  Although a wider bus can deliver more data per clock cycle.
    A narrow bus can often run at a much faster clock speeds.

  Because parallel bus activity is usually state based, 
    All bits must arrive at same time.

  A electrical signal travels approx. 1 foot in 1 ns. 
    So, a 1 GHz clock represents 1 ns. cycle and a distance of 1 ft.
      And in most cases, you want to deliver data in 1/2 clock cycle.
 
  As bus gets faster,
    The slice of time for each line of bus to deliver its payload shrinks.
      Requiring higher quality design and equipment.
      
    Skew - multiple similar lines (32 data lines) don't have identical paths,
       so bits arrive at different times.

      Also, clock is generated from a single point source. This means that
        circuits farther way receive a delayed clock. So, their useful response
        time may actually be less than the clock implies. 

******
  
  As systems get faster, voltage reduced to save power.
     DC resistance.
     Longer lines lose more power.
     More lines draw more power.

  Cross talk 
    AC signaling (frequency)

    Capacitive coupling - parallel lines behave like capacitors.

    When a line becomes charged (bit), the charge force will repels the 
      charge in any lines very close it it.

    Parasitic capacitive coupling manifests when a series of bits traveling 
      in a data line are mirrored in a parallel line (cross-talk). 

    Solutions
      Ground plate or other grounding isolation between lines.

      Lower voltages - weaker signals.

      Avoid parallel data transmission.


  Parallel ATA bus used to connect hard drives to a system.
    16 data lines, 7 ground, and various address, and control lines.
    Protocol used a 40 pin connector.

    As data transfers got faster, the PATA cable had to be modified to 
    prevent cross-talk (capacitive coupling) between lines.

    Each of the standard lines is alternated with an additional ground line
      which then tied into the exiting ground connections on 40 pin connector.

    Drives designed to detect additional lines. If not found, drive controller
      will reduce its data transfer rate.


  Serial bus : uses single pair of complimentary transmitting all bits
    serially.
    
    No skew, bits of word transmitted serially.

    Clock embedded in signal.

    Usually one or two pair of data lines. Easily shielded so 
      no cross-talk. 

    So it can be run at a much higher speed, and higher overall throughput. 
      Twisted pair helps to reduce noise and differential Signaling provide 
        resistant to external noise corruption.

    Paired lines usually function as address, data, and control alternately.

    If power provided, this is done on separate lines.


    Inductive coupling - AC resistance to change in current, more common at higher
      frequencies. But use of differential signaling and very low voltages
      minimizes this.