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Bus
The bus is used to connect the components of the system.
Provides an I/O path between the CPU and the world.
Follows a protocol to provide predictable behavior.
An I/O device (disk, keyboard) requires a controller and
the device itself.
The controller in turn is connected to the CPU via a bus.
Bus protocols.
Properties of a bus are laid out by their protocol.
A protocol is a description of the properties of a system
or device.
Published protocols allow manufacturers to build new devices
that will correctly work with a system.
Some systems use a proprietary bus.
Bus categories - Four sub-types.
Power - used to provide power to the various components.
Address - used by master to select a slave to interact with.
Data - used to transfer data between master and slave
(bi-directional).
Control - used to guarantee correct interaction of components.
Timing - synchronization of components.
Interrupt - service request from slave component.
Arbitration - access negotiation when there is more than 1 master.
Data direction - indicate direction of data transfer (to or from master).
Status/Acknowledgment - reports and notes status of a component.
Protocol specifics include:
Number of lines for each of the sub-categories.
Speed of the bus lines.
Types of control available.
Voltage levels.
Timing limits.
Physical layout of the controller/bus interface.
Bus - used to connect logic units or devices.
Internal to CPU.
Between CPU and immediate circuitry - cache, interface circuitry.
Between CPU and other logic circuits or peripheral interfaces.
Between computer and external devices.
Ports and Buses
Port (interface) - used to connect a single device to the system.
Addressing often not supported.
Minimal controls.
May provide only uni-directional data movement.
Port interface responsible for controlling port lines (master).
Bus - used to connect multiple devices with a common set of lines.
Must provide facilities to distinguish devices (addressing).
Must provide sufficient controls to ensure proper functioning.
Timing, handshaking, data direction.
Must provide bi-directional data movement.
Support circuitry independent of devices using it.
May be provided by interface card or by dedicated circuitry.
Bus issues
Bus - a set of real or virtual lines that connect a system's units.
Real - several separate lines for power, data, address, control.
Virtual - a limited set of lines used for multiple purposes.
Bus shortcomings.
Latency - any delay between issuing an action and the completion. In
a bus - delay that occurs because of distance and intermediate gates.
Propagation delay - an accumulating delay caused when a signal must
pass through a gate.
Skew - signals traveling in a set of lines will arrive at destination
at different times because lines will not have identical lengths.
Attenuation - the loss of the strength of a signal as it travels.
Digital signals tend to round, flatten, and spread.
Inductance and impedance - changing current flow affects itself and
other lines and signals.
Speed and Distance
Bus short comings are amplified by two factors.
A signal travels approx. 1 foot in 1 ns.
1 MHZ = 1000 ns, 100 MHZ = 10ns, 1 GHz = 1ns.
Speed - faster signal changes (higher data speeds) cause skew, propagation
delays, inductance, and latency to become more obvious.
Distance - greater distances cause skew, latency, and attenuation.
Bus classes
Synchronous bus
Clock is provided to signal to all devices when a valid information
transfer can occur (@, data, control).
Simplifies control and interaction between devices.
Requires that devices function a defined synchronous order.
Asynchronous bus
No clock.
Additional control signals needed to guarantee proper interaction.
Devices interact only when and if necessary.
Timing information often embedded in data (lowers data throughput).
Control bus
Control bus provides a variety of signals that provide for proper
interaction of units.
Common controls (not all found on all systems).
Data direction - specified the direction of data movement between master
and slave.
Memory/IO - indicates whether address specified identifies primary
memory or an I/O device.
Bus arbitration (request/grant)- provides correct interaction on
multi-master systems.
Status - used by slave units to indicate their current state or
acknowledge an action by master.
Interrupt - used to request the attention from master.
Clock - provides for synchronization of system.
Misc - example - reset - causes the system to reboot.
Interrupts
Interrupts are used by a client (slave) device to request attention
and action from the master (CPU) unit.
Interrupts are generally prioritized.
An attention request from a hard drive is more time sensitive than
one from a keyboard.
Priority of interrupts are often handled by a dedicated circuit which
delivers a general interrupt request to the master with enough data to
determine interrupt source.
Interrupts come in two forms
Standard or mask-able (IRQ)
Non-mask-able (NMI)
Interrupts
Mask-able or plain interrupts. (IRQ)
Represents conditions that affect activity but not system integrity.
can be ignored.
can be delayed.
can be processed.
Non-mask-able. (NMI)
must be processed (usually represent catastrophic condition).
generated by software.
invalid commands.
illegal memory accesses.
generated by hardware.
hardware failure.
real time critical data transfers.
Bus hierarchy
Processor bus (front side bus)
Connects CPU with controller chips and L2 cache memory.
Speeds 66MHz to 800MHz. (Intel)
Often proprietary. (Intel chip sets)
Newer systems tie L2 cache directly to the CPU and cup speeds.
(back side bus).
Memory bus
Connects memory to CPU (processor bus).
On older machines, memory and processor buses same.
On new machines, actually different buses running at different speeds.
I/O bus
Slower bus or buses that provide a variety of resource control and
interfacing to external devices.
Buses and Ports.
Legacy serial port.
Legacy parallel port.
IEEE 448 Parallel bus.
XT and AT (PC) bus - original bus for the IBM PC.
ISA (Industry Standard Architecture) - generic version of PC bus.
EISA (Extended) - wider data bus, improved speed and control.
MCA (Micro-channel architecture) - wider bus, improved speed and control.
(Proprietary - required licensing from IBM).
Local bus - V-LB (VESA video local bus) - often closer to a port. Used to
connect video card and/or cache to CPU memory. Often proprietary.
PCI (Peripheral Component Interconnect) - wider, faster, greatly
improved control. Protocol public but Intel manufactures most of
the logic chips needed to make it work.
AGP (modified PCI) - used to connect a small number of time/data
critical devices. (Replace VLB).
USB (universal serial bus) - simple physical bus using serial interface
(1 send/ 1 receive) and multi-tasks lines for most bus functions.
When power provided, 2 additional lines used.
Fire-wire - serial bus (SCSI). Independent of specific devices.
Ports
Serial - sends one bit at a time and may have up to 8 control lines.
Parallel printer
Centronics - original PC printer connection. Unidirectional.
IEEE 1284 - major upgrade of Centronics.
Serial
Legacy (com1 com2)
1 transmit line.
1 receive line.
Handshake lines (0-7?).
Ground
Shield
Very slow 120 Baud (part of which was timing/error)
Eventually > 24000 Baud
Parallel
Legacy parallel "Centronics" port. (SPP)
4 control lines
5 status lines
8 uni-directional data lines
8 ground lines
150 kilobytes/sec
SPP improvements
Reverse - has to be supported by software.
Nibble mode - 4 bit reverse data transfer using status lines for data
transfer. Supportable with "Centronics" ports.
Byte mode - Hardware manufacturers redesigned ports to allow software
to disable the data output driver circuits and reverse data direction.
Late model "Centronics" ports.
Bidirectional EPP
EPP - Enhanced parallel port (Pre 1284)
Four modes of data transfer
Data write cycle
Data read cycle
Address write cycle
Address read cycle
Addresses
Channel - distinguish function in a fax/modem/printer.
Commands
Control.
Mixed hardware & software support.
IEEE 1284 - bidirectional ECP
ECP - extended capacity port
Supports addressing, bidirectional data transfers, channels, commands,
status.
Can access printer and modem simultaneously.
Controller has dedicated registers for the various functions.
IEEE 1284
Current systems support IEEE 1284 parallel port.
Usually CMOS configured.
> 1 MB/sec
5 modes
Forward direction.
Compatibility mode - "Centronics" - forward direction only.
Reverse.
Nibble mode.
Byte mode.
Bi-directional
EPP (slight improvement over original).
ECP
Buses
IEEE 448 (CBM specs)
Parallel protocol (technical devices).
Handles multiple devices and bi-directional.
Popular with research scientists and their devices.
8 Data lines
8 Ground lines
5 Interface management lines (control)
3 Handshake lines
15 devices possible on bus
Address hardwired on each device (switches).
Data lines used for both device addressing and data transfer.
Devices can be controller, talker, and/or listener.
Only one controller can be in control at a time.
Controller can pass on control to another controller.
Controller initiates all activity between talkers and listeners.
By specifying their device addresses on data bus.
AT Bus
8/16 bit data.
20 bit address.
6/8 MHz.
Additional interrupt lines.
ISA (Industry Standard Architecture) Bus
Based on the PC (XT) bus.
8 bit data.
20 bit address.
4.7 MHz initially.
7 interrupt lines
+/- 5 Volt for interface circuitry.
+/- 12 Volt to drive mechanical devices such as floppies.
Clock Finalized at 8.33 MHz
Capable of up to 8.33MB/sec transfer.
Clock, I/O, R/W, handshaking, etc.
62 connections.
ISA (AT)
16 bit data.
20 bit address.
8.333 MHz initially.
Interface slots were expanded but were backwards compatible.
============= ======
XT AT extensions
Additional 7 interrupts. (only accessible via the extension slot)
Clock Finalized at 8.33 MHz
Capable of up to 8.33MB/sec transfer.
Added 36 connections for a total of 98.
MCA Micro-channel
32 bit data.
Bus mastering.
Plug and Play - cards no longer needed jumpers.
Different (smaller) interface layout. Not backwards compatible.
IBM enforced its proprietary design with fees.
EISA (extended ISA)
32 bit data.
Bus mastering.
ISA compatible.
Slot is bi-level and ISA cards set deeper in slot to seat on the
correct connectors.
55 additional signals and 35 grounds.
Plug and Play - cards no longer needed jumpers.
Open standard.
More expensive than ISA
And was shortly replaced by local buses such as PCI or VLB.
33 MB/s throughput.
VL-Bus (VESA local bus)
Once CPU > 8MHz., it was separated from the i/o bus.
VL-Bus is an expansion of the ISA bus (again).
Faster.
Used for memory and video access.
Standard ISA still existed on the system.
32 bit data bus.
133MB/s throughput.
Tied into the 486 CPU and used the processor bus directly.
Weak standard - tended to vary with manufacturer.
VESA Local bus. - (video electronics standards association)
VL-bus with a more consistent standard.
1992-1994
Modeled after EISA
112 contacts (many were ground to guard against data corruption).
PCI
1992
Intel driven
Standard public but Intel holds patents on chips that implement protocols
on motherboard.
Evolved over a 10 year period.
32 bit data bus.
33.33 MHz bus.
133 MBps throughput.
Supports both 5V and 3.3V protocols.
Supports PNP.
Burst mode. Once transfer started, bus can provide address control.
Faster versions - 64 bit and faster clocks, but not in PCs.
PCI Express (2002)
Faster - 1, 16, 32 bit bus.
Opposite direction data lines paired up using differential signaling.
Called lanes.
So treated as lanes of serial data buses.
2500 MHz - up to 8000MB/s (sum of both directions).
0.8V signal.
AGP - advanced graphics port.
Not a bus - only one device (video card).
Based on the PCI protocols.
32 bit x 66MHz 266 MB/sec
66 MHz (new versions use doubling of data transfer).
2x 4x and 8x 8x capable of 2133MB/sec
Also supports 3.3 and 1.5 Volt cards.
(cards keyed to fit correct interface).
Although designed to share standard memory
Most current boards have their own high speed memory.
Up to 256MB.
USB - universal serial bus
Serial bus.
USB 1 (1.1) 12 Mb/s or 1.5 MB/s. (slower mode 187.5 KB/s - keyboards).
Capable of 127 devices - daisy chained.
Cable connectors keyed (shaped) to go in one way.
Styles
A - flat - from PC or hub.
B or mini - to device which may be an extension hub.
Cable lengths limited to 5M for high speed and 3M for low.
Hubs can be used to extend distance.
Limit of 5 hubs daisy-chained. Max of 30M.
4 wire cable
Pair of transmit/receive data lines
Power/Ground for low power devices (5 volt).
Data lines used to transmit address, data, and control info.
Plug and Play - auto-configured on the fly.
Hot swappable - all devices can be on when connecting.
Requires support of OS.
USB 2.0 480 Mb/s or 120MB/s. Backwards compatible.
Requires a controller card (primary hub).
PC capable of multiple independent hubs.
Two PCs cannot be hooked together with only USB.
USB Actions
New device ids itself as @0
Hub then assigns an available address to it.
Each device can have up to 16 logical data pipes or channels.
Root hub generates a clock frame once a second +/- 0.05 msec.
Communication between hub and devices done by frames.
USB Frames
Frames consist of 1 or more packets.
Frames can be viewed as a bi-directional session.
All frames are initiated by hub.
Subsequent packets within the frame can move between hub and device in
either direction depending on specific activity.
Four general types of frames.
Control - configure devices, give commands, check status.
Isochronous - used with time sensitive devices - phones, sound. Precise
time intervals but no retransmit on error.
Bulk - large data transfers to/from non-time sensitive devices
e.g printers, Zip drives.
Interrupt - USB does not support device initiated interrupts. Master hub
polls devices for attention need (50 msec).
Frame contains one or more packets of one or more of four packet types
Token - from root
SOF - start of frame.
IN - poll packet asks device to return certain data.
OUT - announces that data will be sent to device.
SETUP - used for configuration.
Data - bidirectional, up to 64 bytes at a time.
Sync field 8-bit.
Packet type id 8-bit.
Data being moved.
CRC cyclic redundancy check 16-byte.
Three types of handshaking
ACK - previous data packet correctly received.
NAK - error (CRC error detected).
STALL - busy (wait).
Fire-wire IEEE 1394 (?)
Based on SCSI
Owned by Apple
Any two or more devices can be connected (no computer required).
Auto-negotiation of bus master.
100-400 Mb/s