Sample ASSIST Output with Dump
Jim Henry Sample ASSIST Output With Dump 1/20/88 (E0 000010) added by R. P. Rannie, 1/89
*** ASSIST 4.0/A2-03/10/02 9672/RB4:OS/390 INS=SDFP7/X=BGHO, CHECK/TRC/=1180, OPTS=CDKMPRX From Penn St Univ & NIU CompSci Dept***
PAGE 1
LOC OBJECT CODE ADDR1 ADDR2 STMT SOURCE STATEMENT
000000 1 TEST CSECT
000000 5810 F010 00010 2 L 1,16(,15) Place 4 in register 1
000004 5820 F014 00014 3 L 2,20(,15) Place 5 in register 2
000008 1A21 4 AR 2,1 Add contents of reg 1 to reg 2
00000C 00000000 5 DC F'0' *** non-executable ***
000010 00000004 6 DC F'4' Data area with initial value 4
000014 00000005 7 DC F'5' Data area with initial value 5
8 END TEST
*** NO STATEMENTS FLAGGED - NO WARNINGS, NO ERRORS
*** DYNAMIC CORE AREA USED: LOW: 1556 HIGH: 192 LEAVING: 457004 FREE BYTES. AVERAGE: 194 BYTES/STMT ***
*** ASSEMBLY TIME = 0.000 SECS, 9000 STATEMENTS/SEC ***
*** PROGRAM EXECUTION BEGINNING - ANY OUTPUT BEFORE EXECUTION TIME MESSAGE IS PRODUCED BY USER PROGRAM ***
*** EXECUTION TIME = 0.000 SECS. 4 INSTRUCTIONS EXECUTED - 4000 INSTRUCTIONS/SEC ***
*** FIRST CARD NOT READ: NO CARDS READ:FILE UNOPENED
ASSIST COMPLETION DUMP
PSW AT ABEND FFC50001 E0000010 COMPLETION CODE SYSTEM = 0C1 OPERATION
** TRACE OF INSTRUCTIONS JUST BEFORE TERMINATION: PSW BITS SHOWN ARE THOSE BEFORE CORRESPONDING INSTRUCTION DECODED ***
IM LOCATION INSTRUCTION : IM = PSW BITS 32-39(ILC,CC,MASK) BEFORE INSTRUCTION EXECUTED AT PROGRAM LOCATION SHOWN
00 000000 5810 F010
80 000004 5820 F014
80 000008 1A21
60 00000A F5F5 0000 0000 -- LAST INSTRUCTION DONE PROBABLE CAUSE OF TERMINATION
(E0 000010) === NOTE: You DON'T get this; it would be next; look at the PSW AT ABEND!
Note that the full word of 0's is after a halfword of F5's. That's because Assist fills memory with F5's, and the AR
instruction only took up a halfword and fullword DC's are always aligned on the next higher fullword boundary (in this
case, location 0C (decimal 12)). So the program blew up when it tried to execute the (nonexistent) F5 instruction, not
the 00 instruction which was coded.
** TRACE OF LAST 10 BRANCH INSTRUCTIONS EXECUTED: PSW BITS SHOWN ARE THOSE BEFORE CORRESPONDING INSTRUCTION DECODED ***
IM LOCATION INSTRUCTION : IM = PSW BITS 32-39(ILC,CC,MASK) BEFORE INSTRUCTION EXECUTED AT PROGRAM LOCATION SHOWN
00 000000 0000
REGS 0-7 F4F4F4F4 00000004 00000009 F4F4F4F4 F4F4F4F4 F4F4F4F4 F4F4F4F4 F4F4F4F4
REGS 8-15 F4F4F4F4 F4F4F4F4 F4F4F4F4 F4F4F4F4 F4F4F4F4 00000018 FFFE7960 00000000
FLTR 0-6 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4 F4F4F4F4F4F4F4F4
Note that registers 1 and 2 contain 4 and 9 respectively, as expected.
USER STORAGE
CORE ADDRESSES SPECIFIED- 000000 TO 000160
000000 5810F010 5820F014 1A21F5F5 00000000 00000004 00000005 F5F5F5F5 00000000 *..0...0...55............5555....*
000020 F5F5F5F5 F5F5F5F5 F5F5F5F5 F5F5F5F5 F5F5F5F5 F5F5F5F5 F5F5F5F5 F5F5F5F5 *55555555555555555555555555555555*
LINES 000040-000120 SAME AS ABOVE
Note that the program is shown in hex; the two 58 (L) instructions, the 1A (AR) instruction, the F5F5 of
ASSIST-initialized memory, and the fullword of 0s created by the DC statement.