Risc - Reduced Instruction Set Computer

The primary function of a computer is to move, compare, or modify a piece of data using simple bit comparison (add/subtract) or shifting (multiply/divide). Each of these functions at its core is very simple activity.

However, they often need to be done many times and complex sequences to accomplish higher level activity in a computer. In order to make the programmer's life easier, computer manufacturers have designed central processing units (cpu) to invoke many of these sequences with individual commands. A computer using one of these is refered to as a Complex Instruction Set Computer - CISC.

A CISC offers an environment where a single command can run a sequence of actions in the hardware of the cpu at speeds much faster than the software equivalent. However, these complex instructions are used less often that the simpler ones and they contribute to the complexity, cost, and reduced overall effeciency of the cpu.

A alternative design known as the Reduced Instruction Set Computer or RISC. A RISC attempts to optimize the speed at which the software runs and provides the programmer with a simple set of instructions and places the burdon of more complex activity back on the programmer. The assumption is that complex instructions are not run that often and if the speed of running simple instructions can be inproved enough, the the occasional block of code needed to simulate a complex command will not slow down the system significantly.

Example:

A CISC runs its simplest command using 4 clock cycles and it most complex command using 16 clock cycles and in a 100 command program, 90 are simple and 10 are complex. So we have 90 * 4 + 10 * 16 = 520 clock cycles.

A RISC runs all commands using 2 clock cycles. However, each of the 10 complex istructions are replaced with 16 RISC instructions. So we have 90 * 2 + (10 * 16) * 2 = 500 clock cycles. This is a small savings but if a program is 100s of 1000s of commands, this starts to accumulate.

Additionally, two other benefits occur from a simple instruction set. 1st, the cpu has a much simpler compact design and can be run at higher speeds (shorter clock cycle) and 2nd, the technique of pipelining can be easily implemented, thus allowing the cpu to process several instructions at the same time.

Main properties of an ideal RISC

• All instructions directly executed by hardwired decoder - Since the number and complexity of instructions have been reduced there is no need for a microprogramable interpreter and hardware offers the quickest way to run an instruction.
• All instructions are of the same size in bytes
• Data bus is the size of the complete instruction - or better a multiple of thus allowing multiple fetches with a single read
• Only direct load or store permited between the cpu and memory. No indirect or compound addresses allowed.
• All operands are references to internal registers or to a standard size offset address for memory
• Simple instruction design makes for easier instruction pipelining.
• Large number of registers available - at least 32, the more registers available, the easier it is to keep the data in the cpu unil finised with it

• Large number of predefined instructions making high level programming languages easy to design and implement.
• Complex predefined instructions run quickly as individual instructions
• Supports microprogramming (microcode interpreting) which
• allows new instructions to be implemented in an exisiting machine in the field.
• allows correcting of an instruction's behaviour on existing machine.
• allows a simpler hardware design to simulate a more complex architecture.