The cpu is known as a state machine. A state machine is a device that makes decision based not only on current input but also on the previous state of the system. Branch on condition depends on condition having been set by a previous action.
The cpu is comprised of several units that can be classified as either logic or storage.
Logic circuits
At minimum, the logic circuits included in a cpu are:
timing control - synchronizes all activity in cpu (indicates when the state of the cpu is to be considered stable).
arithmetic logic unit - performs the basic computation functions.
interrupt logic - handles interaction requests and problems.
instruction decoder - interprets and initiates execution of instructions.
Although we indicate that the decoder functions at the beginning of a fetch execute cycle, it actually is involved throughout the execution of an instruction since it must indicate which resources are interacting in what sequence to complete the execution of an instruction. It is essentially interpreting and executing a program specified by the opcode.
Example. (Mostek 6502) ADC $1024 - adds the contents of an address to the current contents of the accumulator and adjusting it if the carry bit in the condition code register is set.
The decoder first examines the instruction ADC and determines that a 2 byte address is required. Since the 6502 uses an 8 bit bus, the address of the 1st byte (from the Program Counter (pc)) is placed on the address bus, a read and other appropriate control registers are activated, the value retrieved and stored and the pc is incremented. The memory access sequence is repeated to get the 2nd part of the operand. Once both halves of the operand are retrieved, they are combined and placed in the Memory Address Register. A read request is again executed and the value stored at the indicated address is retrieved into the cpu. Once the data is found, the ALU is then activated to add that to the accumulator register. First, the condition code for a carry is checked and the contents of the accumulator is adjusted according. Then the retrieved value is added to the accumulator. If either add caused a carry to occur, the carry flag in the condition register is updated. The cpu then begins processing the next opcode.
Registers
Storage units or registers can also be grouped into user accessible and internal registers. Internal registers are used by the cpu to pass and store intermediate data or state conditions of the machine. User registers are registers that are directly or indirectly manipulated by the user.
Minimum registers needed in a cpu
MAR - memory address register used by the cpu to select other devices via the address bus.
MDR - memory data register used by the cpu to pass or retrieve data to or from an external unit.
IR - instruction register holds the current instruction being decoded and is directly accessed by the decoder.
PC - program counter indicates the next or current instruction (depending on cpu design) to be executed.
GPR - General purpose register used as a scratch area for various instructions.
DPR - Dedicated purpose registers used like GPR except that specific registers are dedicated to particular functions. e.g floating point registers, address index register, counter, or segment register.
On some machines, usually of simple design, most registers tend to be of a dedicated purpose. On other more complex system, there may be both general purpose and dedicated purpose registers. Often, a type of hybrid exists where a register can be used both for some general purpose and also have a certain functionality unique to it or a unique relation to some ISA commands.
SP - Stack pointer used to temporarily store data and/or in support interrupt handling and subroutine features - not all machines have stacks although these are becoming rarer. Although current IBM mainframes have stacks, the concept of stack usage on the 360 architecture was implemented by standard linkage software practices.
CCR - condition code register allows various status issues of the current
state of the system to be recorded via flags for use at a later time. These
are control and status. Control flags indicate how future actions are to
be handled. Status indicate a condition that may need attention.
Examples of condition code registers
Intel 8086
Status
AF - auxiliary carry - a carry from low nibble to high nibble of an 8 bit quantity, used to help support decimal math.
CF - carry flag - there has been a carry out of the high bit of a register often because of addition or multiplication.
OF - overflow flag - overflow of arithmetic results usually triggered by by a carry from bit n-1 to bit n (high bit) and related to signed math.
SF - sign flag - indicates that the result of a arithmetic or logical action resulted in a negative value.
PF - parity flag - the result has an even parity or not.
ZF - zero flag - result of an action was zero (or equal).
Control
DF - direction flag - 8086 has looping commands that implicitly handle the loop counting. This flag is used to indicate whether the count is up or down.
IF - interrupt enable flag - mask or accept the maskable interrupt requests.
TF - trap flag - used by debuggers to cause the system to pause after
each instruction in a program is executed.
6502 ccr
Status
N - negative number - the result of an operation resulted in a negative value in the accumulator
Z - zero or equal results - the result of an operation resulted in a zero (or equal)
C - carry flag - an arithmetic operation caused a 1 bit to shift out of the high bit
V - overflow - a bit has been shifted into the high bit position (used with overflow on signed values)
Control
I - interrupt mask - allow or deny processing of maskable interrupts.
D - decimal mode - perform math in decimal mode
Ibm 360 - uses a register block called the program status word that contains the equivalent of the PC, a set of fields equivalent to the condition code register, and fields specific to the mainframe design.
Channel masks - the 360 architecture uses a system called channels that provide the i/o support for the system. Channels are established by what amounts to support computers designed specifically for i/o. The are programmable with their own ISA. The channel mask allows the blocking of service requests from these devices.
External mask - a mask for an interrupt request from other external devices.
PSW key - used to check whether the current block of code has permission to access a block of memory. Used in a multi-tasking system to protect blocks of memory assigned to specific tasks from being accessed other processes.
BC/EC mode - a flag that indicates that the system is to run in legacy 24 bit address mode or the newer 31 bit address mode.
Machine Check mask - handle or ignore machine (hardware) level problem
interrupts.
Problem state - indicates whether code is supervisor (system level)
or problem (user level). Allows or denies execution of certain commands
and access to certain memory locations.
Interruption code - records the type of interrupt (software) being processed.
Used by the interrupt processing software to determine which interrupt
actually occurred. When a program abends and reports that it
was caused by a SOC4, this information was retrieved from the interruption
code bits in the PSW.
ILC - Instruction Length Code - Indicates the length of the instruction
and its operands just executed.
CC - condition code. The condition code is only 2 bits wide and offers 4
values and is used to note the result of comparisons and arithmetic
operations. 00 = 0, 01 < zero, 10 > zero, 11 overflow or error
Program Masks - offers masking of the software interrupts: fixed point
overflow, decimal overflow, exponent underflow, and significance.
It is possible to write code in a program to handle these conditions in
a chosen manor rather than terminating the task.
Instruction address (PC) - address of next instruction.