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SDRAM - synchronous DRAM
Most ram is asynchronous and will respond as quickly as possible to a
request. So, additional control/status signals required for handshaking.
SDRAM uses internal state machine.
Programmed and predictable behavior. More complex.
SDRAM has many of the same control lines as older ram, except they are
interpreted as opcodes to select an internal routine.
This allows the system's SDRAM controller to better schedule and optimize
memory access, including interleaving of reads/writes so their access
to memory cells does not conflict.
Combined with internal pipe-lining, allows chip to prepare multiple banks
of memory for access ahead of time.
To fit more bits on a chip, the cells have become to small to power the
data bus.
An array of sense amps interface with a row of memory cells (16 Kib).
The amps provide act as a short term latch allowing for reading of the
bit and refresh of the memory cell to occur at the same time.
(sense amp acts as a static latch).
SDRAM modules provide 8 bytes parallel read or write in single access.
Wait state timing might look like 5-1-1-1.
First access still slow.
On slower buses, was not any more efficient than Burst EDO.
SDRAM is capable of working with 83 MHz, 100 MHz, and 133 MHz buses.
SDRAM placed on a module that interfaces an 8 byte (64-bit) data path to the
system bus.
When selecting SDRAM, you need to match speed to your system. You also
need to watch the voltage levels.
In theory, SDRAM of a certain speed should work in a system with a slower
interface if voltages and generic type are same.
RAM was originally 5 Volts. But as bus becomes faster, power consumption
and heat release increases. Because of laptops, a new 3.3 volts memory
has come a standard. And to save power and manufacturing costs, many PCs
now use same technology.
Some systems can adjust to different speeds and voltages. Don't mix.
ECC SDRAM includes extra memory for error checking - most commonly Hamming
Registered memory includes a separate register chip that buffers and drives
the address lines (fan-out). Useful in systems with lots of memory chips.
Standard front-side bus has a limit to number of chips it can drive.
Costs 1 additional clock cycle.
SDRAM - 168 pin (64 bit data) - single data rate, 8 byte wide, one access per
clock.
DDR SDRAM - Double data rate. 2.5V 184 pin. 8 byte wide.
Because the whole row is "cached" in the sense buffer, it is possible
to read/write on both leading and trailing edge of clock cycle.
Requires support of external circuitry.
Additional pins allow for larger memory range.
DDR2 double rate again. 1.8V 240 pin 8 byte wide.
Internally, the ram itself is not faster but more of the row is being
processed concurrently.
Read/write on both leading and trailing edge.
DDR3 (1.5V) 8 bytes wide. Faster bus access.
8-burst-deep. It can have 8 separate 8 byte memory accessed queued up in
static latches ready to transfer. This allows for a faster external bus
without additional waits.
DDR4 is in development.
8 bytes wide.
The different DDRs (DDR, DDR2, DDR3 ...) are not cross compatible. However,
a particular DDR can work in systems designed for a different speed version.
If system is slower, that DDR will slow down. If DDR is slower, it will cause
all of the system memory bus to slow down.
The modules and PCs are (should be) keyed differently to prevent insertion
in wrong style mother board.
PC2400 vs. PC3200, etc. represents overall speed of particular type.
Faster chip should work in slower system if voltages match.
DRDRAM - direct Rambus
Technology designed to compete with SDRAM. Originally against PC133 SDRAM
Faster - Runs on a 16 bit wide bus running at 400 MHz with DDR access.
Module smart, so cheaper design of motherboard(?).
Memory accessed on both edges of clock, theoretically capable of
1.6 Gbytes/sec.
However, Rambus is proprietary (additional cost), technologically more
complex (additional cost and some added latency), runs somewhat hotter.
Also, has greater latency. Slower initial response to read request.
Optimal use when access blocks of memory rather than individual bytes.
Requires custom bus controller.
1996-2005 - at its most competitive.
Used in high-end workstations (CAD) and Gaming Machines (Nintendo 64)
SLDRAM - Synchronous-Link DRAM
Open alternative to Rambus.
200 MHz, 64 bit bus, 2 access per clock.
Rambus ram replaced by XDR Ram - 8 bits/pin/clock - 230 Gbits/sec.
Initial latency eliminated.
Most common in game counsels.
Internally arranges as 8 banks of memory.
Up to four banks could be preparing for read access at same time.
Video RAM
Dual data port.
Interface with PC bus, bi-directional RAM
Interface with video chip (video CPU) serial read-only.
Row refresh (read/rewrite) of dram latched and fed to video chip.
So software can be updating video card memory with latched data being
fed to video at same time.
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