N-Way set associative
  A compromise that takes advantage of both direct and associative caching.

  Composed of 2, 4 or 6 identical direct caches, each containing a slot for
  each line.

  64K cache is often actually arranged as a 4 * 16K set associative cache.

  8 and 16-way set associative caches are being implemented on L2 cache on
    newer CPUs.
     see : https://www.hardwaresecrets.com/how-the-cache-memory-works/9/



  Calculate line id.

  Check tag in each 'way' or slot of target cache line for match.
     If found (hit)
       Use that cached line. 

     Else if not found (miss)
       Check target cache line for empty way or slot.
       If empty way found.
         Use that cache slot.

       Else 
         Use an algorithm to select best way to use.
           Least recently used, # usually best.
           Least used, 
           First in, First out, 
           Random # almost as good as LU or LRU
           etc.

         If data cache and line dirty
           write out.
         Overwrite existing line.

  Searching :
    Search tags in parallel - (true associativity)
     - requires multiple comparator circuits. Fast but large die, more complex.

    Search tags sequentially - (pseudo-associativity)
     - simpler circuitry but a little slower.

  4 line x 2 byte x 2 set Table 


n-Set associative.  
  In this design, we have n fully associative caches.
    Like an n-way set associative where n is very large.
    Each line functions as an associative cache.

  An address is divided into 3 parts [tag][set select][byte in line]

  Each cache is responsible for 1 line(set select).
    Any and all line 0s are randomly stored in cach 0, line 1 in cache 1, etc.
 
  A line of bytes can be put in any line of cache.

  All tags in cache must be checked but cache is 1/n is size,
    so total search is smaller.