Direct Cache
  Lines in main memory are mapped to identical line in cache.
    Any line zero from any segment will go into line zero of cache.
    Only one line zero can be in the cache at a time.
 
    Some newer designs hash the tag and line to "randomize" the line to use.
      Slows cache access some but reduces line competition.

  Easy to implement.

  Good performance if cache is very large > 512 KiB

  May provide poor performance in systems using virtual memory.

  Poor performance in systems that support intense multitasking.
    

  Segment id (Tag) = int( mem@ / cache size ).

  Line = int ( (mem@ % size of cache) / line size ).

4 line x 4 byte Table 
8 line x 2 byte Table 
2 line x 8 byte Table