Cache Levels
  High speed memory - usually static ram (flip-flops).

  Level 1 - part of CPU
    16 to 64 KB (per core)
    Spit cache - instructions and data is separate cache units.

  Level 2 - external to CPU but on high speed local bus
    512 KB to 8 MB (* # of cores).
    Unified cache.
 
    Placed on CPU chip or interfaced with modern bus controllers 
      - Hypertransport and Intel QuickPath Interconnect
        provide near CPU data throughput.

    On multi-core CPUs, my be shared or separate cache for each core.
      Shared - requires more wiring but single combined cache usually 
        bigger and reduces stale data.
        Stale data occurs when one core modifies common data in its  
          and copies in other core caches not in sync.
        Also, each core can use as much or as little of cache as needed
          up to full use.

      Dedicated - simpler design, fewer 'wire', less competition for
        target lines but increases chance of stale data.

        Limits total available memory in cache.
 
  Level 3 - static RAM with no waits. 
    8 MB common(?)