Implementation of a direct cache.
  Direct caching is the simplest form of caching.

  Cache size is chosen.

  Main memory is parsed into cache sized blocks called segments.
  
  The cache and each "segment" of main memory are broken up into smaller 
    fixed size units called lines. 

  A cache line length is usually some multiple of the data bus width that 
    offers the fastest sequence of accesses. 
    64 bytes is common on modern CPUs.

    Remember : modern DDR SDRAM is 64-bit (8 byte)
      and capable of 8 accesses in rapid sequence.

  Check out :

   mechanitis.blogspot.com/2011/07/dissecting-disruptor-why-its-so-fast_22.html

  * This site has an interesting discussion cache, line size, and multi-thread
    programs (programs that attempt to use multiple cores)

  
  When a byte/word in main memory accessed.

    The main memory segment it is found in is determined.

    The line in that segment in which the target resides is determined.

    The tag field contents of the matching line in the cache is 
      matched against the segment ID.

    If matched,
      the line of memory in that cache line is accessed by the CPU.

      This is referred to as a 'hit'.

    If no match,
      the line of storage in main memory read into the line of the cache.

      The tag field is updated with the segment ID of the line just fetched. 
 
      The addressed memory cell is cache is made available to the CPU.

      This is referred to as a 'miss'.
      
      Note that the whole line from main memory is copied to the cache line.

      Different lines in the cache can and may be from different segments 
        in memory.

    Depending on cache design, memory writes may be handled differently.

  A cache line consists several fields.
   Tag field - records the segment id.

   Valid flag - indicates contents valid data, system 1st booted or if cache 
     controller clears non-active cache lines in preparation for later use.

   Dirty flag - if data cached, has the data been modified.
     Dirty bit not needed on an instruction cache.

   Data - actual bytes of data.

  * Other cache designs may have additional fields.