CPU instruction design issues.

Instruction design is affected by a variety of issues.

How data is stored and manipulated in the cpu.
  Stack
  Accumulator - set of limited purpose registers.
  General Purpose registers 

Number of operands per instruction
  Zero, one, two, and three common.

Operand access - where data addressed by operand is.
  Register to register.
  Register to memory.
  Memory to Memory - in most cases a register needs to be used.

Type and size of operand
  Memory address
  Data
    Numbers, integer or float
    Characters

Operations - what kind of activity is to be invoked.
  Arithmetic
  Logical (test)
  Data Movement
  Conversion 
  

Other issues

Short instructions
  Quicker to fetch.
  Quicker to decode.
  Limited number of specifiable actions and operands.

Fixed length instructions
  Easy to fetch and decode
  Wastes space (Marie skipcond instruction)

Memory organization affects format.
  If memory accessed as 16 or 32 bit words,
    accessing individual characters may be complex or waste memory.

  Many systems retain byte addressable addressing
    even if access costs additional clock cycles

  May require instruction and/or data alignment on word boundaries.

Addressing mode
  How flexible is the addressing mode to be.

  More flexible - slower, longer but more done with single instruction.

  Marie had only memory direct and indirect. 

  Ordering of operands 
    If multiple operands, source or destination named first.

    Note that the assembler software will usually follow the opcode/operand
    structure but does not have to. 

  Number of and type of registers in cpu. How are they used. 
    IBM 360 16 GPR used for both data manipulation and addressing. 

    Intel 4 GPR with some special purpose assignments, and several DPRs,
      some of which only hold address informaton.

    MOS Technology 6502 1 GPR and 2 index registers with some additional useage.


How data is stored inside the cpu.

  Stack style Operands found on top of memory stack.
    If internal, 
      expensive but very fast.

    If external, 
      slow but economical.

    Short, simple, dense instructions. 

    Simple to access.
      But only top element available, requiring careful program design.


  Accumulator type 
    Only a few GPR (often 1) with possibly a few support registers.
    
    Operand easy to find. 

    Fairly simple small instruction set. 

    Simple overall cpu design. 

    Tends to use register/memory access 
      May use several primary memory accesses to perform task.

    Resulting in long programs and slow execution. 


  General Purpose registers. 
    Operands store in any of several registers. 

    Fast easy access to operands, since often in GPRs. 

    Instructions longer, more complex as each register must be recognized. 

    More complex and expensive cpu design. 

    With current pricing still most popular. 


Length of instructions. Fixed vs Variable 
  Fixed length 
    Easy to retrieve and decode, often opcode and operand in single fetch. 

    May limit number of different opcodes or operand types. 
  
    May waste memory. If 4 byte opcode/operand structure to instruction 
    but some instructions only need 2 bytes to be complete, other two
    bytes not used.

  Variable length 
    Slower to decode, 
      both because of possible complexity of instruction and because 
      decoder more complex. 

    More efficient use of memory. 

    Provides for more complex instructions and different addressing modes. 

  Compromises 
    Often limited to 2 or 3 instruction lengths to be multiples of bus or 
      word size.

    Expanding opcodes 
      Variable length opcodes for a given length instruction. 
        16 bit instruction - 1st 2 bits specify opcode length (4 length) 
        00b - 2 bit opcodes or 4 instructions with 12 bit operands.
          Load, store, direct and indirect. 

        01b - 6 bit opcode or 64 instructions with 8 bit operands. 
          16 GP Register machine allowing register to register action. 

        10b - 9 bit opcode or 512K instructions with a 5 bit operands.


Number of operands. 
  Zero - often designates activities implicit to particular registers. 
    CLC - clear carry bit of condition code register.

  One - often an address and implies action between memory and a specific
  cpu register such as the accumulator (cpus with limited registers). Most
  of the Marie instructions. Or if a register, implies specific action,
  such as incrementing contents of a named GPR. 

  Two - two registers or a register and memory. Most commonly seen in 
  GPR machines where user must choose. 

  Three or more - combination of registers and memory. 
  Complex addressing modes. L R1,23(R3) (4 operands) 
  Complex instructions where source, destination and size specified. 

  It is possible to have a zero operand only instruction machine. 
    Usually a stack based machine where all action apply to the top 1 or 
    two storage locations of the stack.  If additional operands are needed 
    they are placed on the stack like data. So if you wanted a stack machine 
    that could reach down into the stack and rotate a value up to the top, 
    you place the depth of the needed value on the top of the stack and 
    execute the rotate opcode.