CPU instruction design issues.

Instruction design is affected by a variety of issues.

Type of data being manipulated and granularity (size of data units)
  Bit - special instructions that CPU flags.
    Instructions that take mask arguments for targeting bits 
      in work registers or memory.
    
  Boolean - bit manipulation (of register or memory)
    Logical AND, OR, XOR
      Applied to whole byte or word in register or memory.

    Affects flags differently than math. 
      Zero and Sign, but not Carry or Overflow

  Nibble - 4-bit, accessed via masking, where instruction operand specifies 
    which bits to work on. Some instructions may have half byte modes for
    register manipulation commands. Also BCD style instructions.

  BCD - custom instructions to work with binary coded decimal and use
    alternative flags in CPU.
    Example : IBM 360 Pack instructions 

  Byte - generally smallest working unit directly addressable by instruction.

  Word - 16, 32, or 64 byte manipulation.

  String - consecutive series of storage locations.
    Examples : 
      IBM 360 Pack instructions.
      Intel loop instructions.

  Integer - 16-bit, 32-bit, 64-bit sizes. Slightly different instructions
    for each, so overflow/sign handled correctly.  

  Float - IEEE standard 
    Separate instructions and registers. 
    Often separate processor core on chip.

  Boolean - bit manipulation (of register or memory)
    Affects flags differently than math. 

    Custom instructions for targeting CPU status flags.

    Masks for targeting bits in work registers and memory.

  Addresses - direct and pointers.
    Valid ranges
      IBM 360 
        GPRs 32 bits when viewed as data..
        R0 treated as null if used as address. 
        BC mode recognizes only 24 bit-address
        EC mode recognizes only 31 bit-address

      ARM 
        32-bit indirect (register held) address. 4 GiB address range.
        23-bit signed Word(4-byte) aligned offset (operand)
          Giving +/- address range.
          Note that 

      Intel x86
        uses segment registers combined with
          Instruction pointer
          Stack Pointer
          Base pointer
          and possibly index register so arrive at a target address.
 
    Custom instructions to address alternative buses.
      Intel x86
         IN and OUT that address CPU port interace pins rather than
         memory address/data pins.
      IBM 360
        channel instructions 
 
Size of instruction and operands.
  Variation in size and number of operands requires opcode to indicate 
    if additional fetches needed to obtain full instruction.

  RISC limits instruction to single standard size.
    Fetch is single action.
    Not required to use all bits of instruction word.

Addressing mode
  Variety - different types of addressing (effective addressing).

  Orthogonality - addressing mode independent of register used or function.
    If you have 16 work registers - a particular addressing mode can use 
      any register (or combination of). Requires additional bits in opcode.

Complexity of instruction.
  Instruction may performs complex task and use compound addressing (CISC)
    Improved code density.

  Instruction performs single simple task (RISC)
    Fetch/store against memory dedicated task. 
    Improved overall speed performance, pipe lining, and decoding.  

How data is stored/processed inside the CPU (work registers).

  General Purpose registers - quantity.
    Limited Accumulator type vs. Register Files

  Dedicated purpose registers - assigned specific tasks.

  Stack style Operands found on top of memory stack.

Actions
  Data movement.
    Register to register
    Register to/from memory.
      Direct or indirect (effective address)

  Data conversion
    convert data1 to data2 
    - expands/contracts data1 to data2 while honoring format
      signed integer, float
    - convert and pack ASCII/EBCDIC character representation of decimal
      values to BCD (packed) sequences.
    - some newer CPUs support 

  Math 
    Integer addition, subtraction, multiplication, division.
      Not all operators may be supported on a particular CPU architecture.
 
    Float - note that float is often performed in a dedicated processor
      core. 

  Stack manipulation.
    Stack is a dedicated area in memory used as temporary storage. It is 
    usually accessed with dedicated register, stack pointer, and data is 
    pushed/popped on and off the 'top' of the stack with this register.

    Key aspect of a stack is that you 'always' work from the 'top' of the 
    stack.

    Various CPUs offer instructions to manipulate the stack contents.
      Although specific instructions vary with architecture.
      push, pop, rotate, duplicate. 

    Intel offers a 2nd register than can be used to access the contents
      of a stack out of order with affecting the stack pointer.

    The stack is also used to store return address for calls and interrupts.

    See also : Stack machine

  Custom processors exist. 
    Graphics processor
      advanced version of floating point processor combined with circuitry 
      to drive an external display.

    Digitial Signal Processor (DSP) k
      coverts between streaming data, often analog, and digitial encoding, 
      often in real-time.
     
Flow of control - instruction alters Program Counter (IP)

  Branches and Jumps
    Relative to current PC value.
    Absolute address.
 
  Functions - jump and return (user defined code).
    
    6502 - JSR
      Pushes the current PC (pointing to next instruction) onto
      stack in low/high order and sets PC to specified address. 

      RTS (return from subroutine) pops bytes off of stack, and places them
        in program counter.

    80x8 - Call
      included a number of ways to identify the target routine's address.
        near/far relative -signed offset
        near/far absolute regiser indirect - target address in register
        near/far absolute memory indirect - target address in identifyed memory
        near/far absolute address - target address in operand

      Near :
        Pushes program counter (return address) onto stack before call.

      Far :
        Pushes code segment register and program counter (return address) 
        onto stack.

      RET : return from, used different opcode for near and far.


    IBM 360 - no user stack, so stack simulated with linked list.
      * Standard linkage.
      BALR R14,R15 - branch and link - right 32-bits of PSW, next instruction's 
      address, stored in R14 and @ of target location specified by R15.  

        R0  - will hold any return code set by subroutine.
        R1  - holds a single value to be passed or the address of a list of
              parameters. Called routine decides.
        R13 - pointer to save area where subroutine can store any GPRs before
              altering them.
        R14 - return address of next instruction when execution returns from
              subroutine.
        R15 - address of subroutine.

        Subroutine will reload saved GPRs right before returning to caller.
 
      BR R14 (branch to register specified location) returns execution to @ 
      specified in R14. 

      The use of the noted registers is strictly a traditional protocol. 
      IBM 360 hardware does not restrict activity based on register choice.

   Interrupts