Interaction with I/O

  Programmed I/O - PIO  - handled by CPU

    Pole driven.

      All interaction initiated by CPU
        CPU poles a defined list of devices.

      Scheduled interrupt may be used to initiate pole.

      Simplest to implement but most CPU intensive.

      Limits throughput because all devices need to be poled in a given 
        time-period.

      Minimal external support circuitry required.

      Inexpensive systems, simple interrupt but CPU intensive.

      Examples :
        C64 - used an interrupt tied to AC. Every 60th of a second,
          it would pole several I/O interfaces.
            Keyboard, serial port, storage device port, etc.

          # in Europe, this was every 50th of a second.

        Alarm systems, if sensor line lost (damages or on purpose),
          pole driven guarantees controller discovers it.

        USB - single pair lines to move data in serial manner.
          Used for address, data, and control.
          All interrupt activity initiated by controller to prevent packet
            collision on data lines.

    Interrupt Driven I/O  (Still PIO - CPU has to move data)

      I/O devices can request the attention of CPU with an interrupt at any
        time, but does so only when needed.

      CPU can dedicate extended time for particular device or program.
         With IRQ masking, this time can be extended.
 
      CPU does not have to check in on I/O that does not need attention.

      CPU can prioritize, delay processing, or possibly ignore I/O request.

      Because multiple interrupt sources can exist, often uses external
        circuitry.  e.g 

          Programmable interrupt controller

          (8086 Intel) 8259A PIC.

          APIC - interrupt controller for multi-CPU systems. 

          (ARM) General Interrupt Controller

         PIC receives and prioritizes incoming interrupts.

         PIC sends single interrupt to CPU.

         CPU communicates with the PIC to identify requesting device.
           (If/when convenient)
 
         CPU processes interrupt and goes back to original work.

         * CPU often has separate pins for mask-able and non-mask-able IRQ.

    CPU still has to handles data transfer. 

  I/O handled by dedicated Channel I/O controller. 

    Newer systems - CPU hands off transfer of data to secondary controller,
      which only interrupts CPU on completion of task or if problem.

    CPU requests the controller initiate an I/O task.

    Controller then performs all I/O between memory and I/O device.
      Devices send IRQ (interrupt requests) to controller which handles
      most interrupts.

    Controller uses interrupt to signal success or errors to CPU.
      Does not eliminate CPU interrupts but greatly reduces them.

    CPU may use port mapped I/O to program or initialize task controller
      is to perform.  

      Intel - IN and OUT instructions used to send request to DMA chip.

      IBM 360 - the SIO instruction to program Channel controller and 
        start task.

   The controller uses designated block in main memory to store or retrieve 
     data being moved.

    Direct Memory Access controller. (Lower end systems)
      Handles I/O interaction without the intervention of the CPU after initial
        CPU interaction. 

      Requires separate arbitration protocol - shares buses with CPU.

      Predefined standardized tasks.

      CPU NOT occupied but may have to compete for resources.

    Channel I/O (Mainframe or Supercomputer) (DMA with a brain)
      Secondary device / CPU.

      CPU simpler (cheaper, often RISC) in design than main CPU.

      Programmable. (Difference from DMA).

      After being programmed 
        Moves data between memory and I/O device independent of main CPU.

      Runs in parallel to CPU.

      Provides multiple channels - can control many devices. 

      Memory access designed to be more efficient than on small systems.

    # Commodore drives used 6502 CPUs - part of channel i/o on devices.
  
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