Input/Output - Chapter 7
All data manipulation not directly performed in the CPU or between CPU and
primary memory is I/O.
Resources needed in the system for I/O
Protocol - set of standardized rules for consistent interaction between
system and i/o devices, including
physical properties
of media
of interface
access methods
timing methods
timing standard
data encoding
data formats
error detection and recovery
Interface between I/O and CPU.
Memory mapped vs. port mapped vs. channel (including DMA).
Wikipedia : Memory-mapped_I/O and Channel_I/O
Buses, cables, and interfaces.
Control modules in both host(system) and peripheral devices.
Provides signal translation, timing support, physical control, etc.
(Early CD-ROMs often coupled to audio card).
I/O control methods -
CPU controlled
Memory mapped :
Interface to the I/O is treated as a set of primary memory locations.
Software drivers determine meaning of data stored or retrieved.
- Loss of some memory space (8086 - 300K) because it is reserved for
I/O interfaces. Less important with 4GiB address space.
+ All instruction modes available
- May slow overall memory bus access down.
* Cache architecture alleviates this.
- Can limit or complicate contiguous memory range.
Original x86 architecture had a 1MiB boundary because I/O was mapped
above 640K.
* Virtual memory on modern systems solve this issue.
Port mapped :
CPU has separate set of instructions that access specific pins
on CPU that act as ports or that cause a demux to connect portions
of the address and data pin-outs to a different set of lines tied
to i/o devices.
+ Separate bus tied to I/O devices. CPU can go back to using memory
bus while I/O devices prepares response on separate lines.
Run out of order instructions
and/or
Cached instructions.
- Adds complexity to CPU design and motherboard.
- Often limited set of instructions using specific CPU registers.
May need to write to memory before other actions can be taken.
Channel I/O : see below
**** Interaction with I/O :
Programmed I/O - PIO - handled by CPU
Pole driven.
All interaction initiated by CPU
CPU poles a defined list of devices.
Scheduled interrupt may be used to initiate pole.
Simplest to implement but most CPU intensive.
Limits throughput because all devices need to be poled in a given
time-period.
Minimal external support circuitry required.
Inexpensive systems, simple interrupt but CPU intensive.
Examples :
C64 - used an interrupt tied to AC. Every 60th of a second,
it would pole several I/O interfaces.
Keyboard, serial port, storage device port, etc.
# in Europe, this was every 50th of a second.
Alarm systems, if sensor line lost (damages or on purpose),
pole driven guarantees controller discovers it.
USB - single pair lines to move data in serial manner.
Used for address, data, and control.
All interrupt activity initiated by controller to prevent packet
collision on data lines.
Interrupt Driven I/O (Still PIO - CPU has to move data)
I/O devices can request the attention of CPU with an interrupt at any
time, but does so only when needed.
CPU can dedicate extended time for particular device or program.
With IRQ masking, this time can be extended.
CPU does not have to check in on I/O that does not need attention.
CPU can prioritize, delay processing, or possibly ignore I/O request.
Because multiple interrupt sources can exist, often uses external
circuitry. e.g
Programmable interrupt controller
(8086 Intel) 8259A PIC.
APIC - interrupt controller for multi-CPU systems.
(ARM) General Interrupt Controller
PIC receives and prioritizes incoming interrupts.
PIC sends single interrupt to CPU.
CPU communicates with the PIC to identify requesting device.
(If/when convenient)
CPU processes interrupt and goes back to original work.
* CPU often has separate pins for mask-able and non-mask-able IRQ.
CPU still has to handles data transfer.
I/O handled by dedicated Channel I/O controller.
Newer systems - CPU hands off transfer of data to secondary controller,
which only interrupts CPU on completion of task or if problem.
CPU requests the controller initiate an I/O task.
Controller then performs all I/O between memory and I/O device.
Devices send IRQ (interrupt requests) to controller which handles
most interrupts.
Controller uses interrupt to signal success or errors to CPU.
Does not eliminate CPU interrupts but greatly reduces them.
CPU may use port mapped I/O to program or initialize task controller
is to perform.
Intel - IN and OUT instructions used to send request to DMA chip.
IBM 360 - the SIO instruction to program Channel controller and
start task.
The controller uses designated block in main memory to store or retrieve
data being moved.
Direct Memory Access controller. (Lower end systems)
Handles I/O interaction without the intervention of the CPU after initial
CPU interaction.
Requires separate arbitration protocol - shares buses with CPU.
Predefined standardized tasks.
CPU NOT occupied but may have to compete for resources.
Channel I/O (Mainframe or Supercomputer) (DMA with a brain)
Secondary device / CPU.
CPU simpler (cheaper, often RISC) in design than main CPU.
Programmable. (Difference from DMA).
After being programmed
Moves data between memory and I/O device independent of main CPU.
Runs in parallel to CPU.
Provides multiple channels - can control many devices.
Memory access designed to be more efficient than on small systems.
# Commodore drives used 6502 CPUs - part of channel i/o on devices.