Lecture
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System architectural views.
(modeled on ISO/OSI 1977
- international standards organization/open systems interconnection )
a. Physical level (Digital logic). - L0
b. Micro-architectural level. - L1
c. Instruction set architecture. - L2
d. Low-level programming. - L3
e. Operating system level. - L4
f. High-level programming. - L5
g. Application level - L6
h. Application level programming - L7
Physical level - L0
[CSCI 463]
Base level
Voltage levels, signal timing and clock speeds, path distances.
Physical materials.
Binary, analog, multiple discrete levels (Flash memory 4 value per cell)
Basic (atomic) logic units called gates:
Bit level memory.
Simple decision circuits (NAND, NOR, NOT).
Simple functional circuits:
Standard memory units - registers, byte or word sized memory cells.
Simple computational units - adder circuit, comparator, shift multiplier.
Micro-architectural or control level - L1
[CSCI 463, CSCI 480]
Functional units arranged from physical material.
Memory units assigned specific function:
Memory address registers, memory data registers, accumulators,
cache, general purpose registers.
Computation units:
Arithmetic Logic Unit (ALU).
Group adder, multiplier, comparator together.
SIMD - single instruction, multiple data
* Floats often done by separate core or GPU (graphical processor unit).
Instruction Decoder - logic to select calculating function.
Hardwired or programmable decoding and execution.
Instruction may be decoded either.
By a hardwired decoder.
RISC : simpler logic makes for easy implementation.
+ faster execution.
- complex actions performed at software level.
By a programmable decoder (micro-interpreter).
CISC : used on more complex CPUs.
+ define complex instructions at hardware level.
+ allows repair or upgrade.
- not all gates in use for particular instruction.
- slower than hard-coded design.
Modern Pentium/AMD chips are at least partially micro-programmable.
Memory Management Unit.