Lectures
Putting it together
  a. Combining flip-flops and a decoder circuit give a memory chip.
  Below is a 4 word 3-bit memory bank.


I0, I1, I2  - input data lines 0,1, and 2. Bits arranged in column.
   Used to write data to a memory row.

A0, A1  - 2 bit address 2^2 gives 4 rows of 3-bit data
   Addresses 00, 01, 10, 11

O0, O1, O2  - output lines for reading bits out.

CS - chip select, external signal to select this 12 bit bank of memory.
 
RD - read request. Activates output data lines. 
NOT D - sets chip to do write to memory flip-flops.

OE - output enable. Actives special tri-state (or three-state) gateway.  
   Besides 0 or 1, can assume a high-impedance state.
   Looks as if it doesn't exist. 


Write 
  A0 and A1 address lines are combined (decoded) to select 1 of 
    the 4 data rows.

  CS set high. RD and OE set low. 

  CS AND !RD are combined and then ANDed with the select lines at the 
    write gate and sent to the CK input (enable) to activate one row 
    of flip-flops which will receive data from I0-2.
    All other rows stay latched.   

  With OE set low by memory control, output lines, O0-2, are in 
    high-impedance mode. Disconnected from the data bus.

Read
  CS and OE set high, RD set low.

  CS AND !RD sent to AND gates connected to CK (enable) which in turn
    signal all flips-flops to remain latched and ignore any input.

  CS AND RD AND OE are also routed to the tri-state gates to enable them
    for output. 

  A0 and A1 are decoded and result is sent to AND gates tied to the output
    side of the flip-flops. Only bits in one row selected.