Separate clock line for timing.

5 volt.
+/-12 volt provided for power for interfaced devices.

4.7 MHz, 8 MHz, 10 MHz

Devices unable to respond in time, such as memory, may exert a wait, which stalls CPU.

Or a device may 'disconnect' from bus and use the interrupt lines to request attention when ready to respond to assigned task.

Bus mastering is supported.

Does not support burst mode, each read or write treated as an atomic task.

Control/handshaking signals pull-up or pull-down.
No voltage lever defined (5 volt most likely).

Devices use data lines for any device level control/status communication.

User is bus master. This technically means bus mastering is supported.

A device can be a :
initiator - initializes the task (data transfer)

talker - sends data
listener - receives data

There can be only one of each but a device may be both a talker and initiator, a listener and initiator, or just one of these three.

Only one task can be performed at a time. It must be terminated in some way before another task begun.

Because there is no clock, these are maximum possible speeds.

Burst mode supported

Once a device is selected and activated, data transfer is performed until data transferred or error condition occurs.

5 volt signal.

Reflected-wave switching.

No clock signal.

It is possible to directly wire a device via a dedicated bus directly to the controller, in which case much higher throughput is possible. Common practice with video controllers.

4-bit command/data mask lines.

4 interrupt lines (current versions use message signaled interrupts transmitted on data lines.

Each interface has its own arbitration request/grant lines.

5 volt signaling.

Some additional control lines

Uses a 16 bit ID (BDF) to recognize devices :

• 8-bit bus ID (256 buses)
• 5-bit device ID (32 devices)
• 3-bit function ID

Transaction based.

Initializes a transaction by providing a device target address and a 4-bit control command.

Followed by 0 or more byte transfers. May use command/mask lines to narrow and/or select which 8 bits of 32 bit bus carries data.

Only one transaction can be performed at a time over a bus. A transaction may complete, error out, or be suspended, but cannot be interleaved among different devices on a bus.

The PCI controller may talk to multiple buses at the same time as long as they are not daisy chained.

Burst mode supported.

Transfer of up to 4 bytes at a time. Maximum burst size limited by resources of sender and receiver.

PCIe 1.0, 2.0 uses 8b/10b RLL
PCIe 3.0, 4.0 uses 128b/130b RLL

These are ideal transfers. They are dependent on the device's response time, the size of the transfer.

Two pair of lines transmitting data in opposite directions makes up a lane.

All device address/data/control transferred over lanes.

An interface has at least 1 lane but may have up to 32 lanes.

A byte of data is serialized and transmitted over a single lane.

But a series of bytes may be interleaved over several lanes if available

Each device interface is dedicated and assigned its own bus ID, buses are not shared.

Optional reference clock pair provide, but use not required.

A packet can contain 0 (control) to 64 bytes of data. It is encapsulated in a transaction layer packet which in turn is placed into a data-link layer packet.

Data-link layer packets contain device addressing, sequencing (for lane usage), data, and error check (LCLC) information. Used by PCI controllers router to route to correct bus/device successfully.

Transaction layer packets contain portions of the transaction being performed. This allows the controller to interleave/perform multiple transaction at the same time. Because each bus is unique to a device, not conflicts.

Burst mode supported.

Transfer of 1 to 32 bytes of data at a time based on available lanes.
Maximum burst size limited by resources of sender and receiver.

Uses NRZI and differential signaling.

USB 1 & 2 :

Uses bit stuffing, zero stuffed into bit stream after 6 consecutive 1s.

Half-duplex, transmits only in one direction at a time.

USB 2 : -10 mV to -10 mV low signal, 360 mV to 440 mV high signal.

USB 3. :

uses 8b/10b encoding.

Extra pair of data lines, Full-duplex can transmit in both directions.

• LS (low-speed) 1.5 Mbit/s (keyboard, mouse, etc.)
• FS (full-speed) 12 Mbit/s (printers, storage, etc.)

• HS (high-speed) 480 MBits/s (storage)

• SS (super-speed) 5.0 Gbits/s (ssd storage)
• SS+ (super-speed+) 10 Gbits/s, 20 Gbits/s using 2 lanes (USB 3.2)

Assumes point to point connections, but hubs can interface with multiple devices and route packets.

All transactions initiated by the controller. i.e bus mastering is NOT supported.

Uses frames consisting of one or more packets.

A frame is a particular task or transaction,

• Transmit data
• Retrieve data
• Check device Status
• Discover/initiate a device
• etc.

Low, full speed frames(task) must run to completion.
High speed (USB 2) can be split and resumed later.

USB 2 and up support burst mode. (according to USB.org)

Low speed (USB 1.1) : 8 bytes/packet
Full speed (USB 1.1) : 8,16,32, or 64 bytes/packet.
High speed (USB 2) : up to 512 bytes/packet.
SuperSpeed (USB 3) : up to 1 KiB/packet.

Differential signaling
+/- 250mVolt

8b/10b encoding. Unassigned 10b patterns used for control status communication between end points.

version	raw data	encoded data
1 8b/10b	1.2 Gbits/s	1.5 Gbits/s
2 8b/10b	2.4 Gbits/s	3.0 Gbits/s
3 8b/10b	4.8 Gbits/s	6.0 Gbits/s
3.2 128b/130b	1969 MB/s	16 Gbits/s

7 line shielded data cable.

• 2 pair of differential data lines
  transfers in each direction.
• 3 ground lines

Implements the ATA (AT attachement) protocol over a serial interface.

A drive cannot initiate a transaction. i.e bus mastering NOT supported.

Packet based communication between endpoints called a File information structure (FIS).

Supports Native command queueing, which allows controller to rearrrange disk access requests for best performance.

Burst mode supported.