Reading : Instruction cycle

The basic fetch and execute cycle of a von Neumann or stored program computer.

  Key feature - memory holds both instructions and data.

  Instruction pointer (program counter) indicates location of instruction.

An instruction consists two parts :
  Opcode - indicates what task is to be performed.

  Operand[s] - indicates source of data to be acted on is 
               and where results stored.


Program counter (PC) - incrementing pointer may occur immediately after 
    fetch of instruction (during execution). More common.

  Or after instruction completion and just before fetch of next instruction.

  Exact implementation depends on CPU design.

Memory Address Register (MAR) - holds address of external memory being 
  referenced. Interfaces with the external address bus or CPU cache.

  Always written by the CPU.

  Harvard architecture has one for code and one for data.

Memory Data Register (MDR) - holds data being read/written. Bi-directional.
  Occasionally referenced as memory buffer register or MBR 

  Harvard architecture has one for code and one for data.

Instruction Register (IR) - register that holds current instruction being
  executed. This is the register the instruction decoder is reading.

Control Unit (CU) - circuity that decodes the instruction in the IR. 
  Complexity varies greatly between architecures.

  RISC - simple, fast, very few or no stages.

  CISC - complex, multi-staged, may be reprogrammable.

Arithmetic Logic Unit (ALU) - performs mathematical and logical operations.
  Usually only integer based and variety of operations vary greatly between
  CPU designs. 

Floating Point Unit (FPU) - performs more advanced floating point operations.
  Optional?

* Graphics Processor (GPU) - performs operations including floating point 
  operations required for advanced graphics. 

  In modern systems, the GPU has replaced the FPU. 

  In supercomputers, the GPU is not attached to a video display 
    but is used purely for its computational power.


Executing code

Code execution follows a basic pattern. However, the exact implementation
may vary based on the CPU design.

From wikipedia 

While running.
  Fetch step 
   - Copy the PC into the MAR.
   - Copy instruction from memory into MDR.
   - Copy instruction into Instruction register.
     # CPU assumes it is fetching an instruction.
  
  Increment Program counter.

  Decode instruction.
   - determines which circuits to use.
   - determines if additional information (operands) need to fetched.
     - fetch operands and adjust program counter. 

  Read effective address (where data is).
   - Instructions often hold arguments (operands) 
     Operands may be 
       actual data to use. 
       address in memory where data resides or will be put.
         (direct memory operation)
       address in memory that contains an address of the data.
         (indirect memory operation)

  Execute step.
   - performed the requested action, most likely involving the ALU.
   - But could be changing the PC to jump to different block of code.
   - May be as simple as loading data into a CPU register.
   - Or setting or clearing a CPU status flag.

# Version targeting one of the early 1980s 8 bit data bus CPUs.

Initialize Program Counter (PC) to start address of program in memory.

While running program
Do
  Address memory and fetch instruction opcode from memory into instruction 
  register via the MDR

    Increment PC

  Decode instruction opcode to determine task and if any additional operands
    required.

  While instruction operands are required 
  Do
    # More common in CISC architectures.
    Fetch operands (and store in temporary CPU register).
    Increment PC

  Endwhile

  Execute instruction.
  
    If operand is pointer, additional memory fetches may be performed.
      These normally do not affect the PC.
      But they do tie up the address and data buses. (bottleneck)

    Exception are flow of control instructions such as :
    - jump or branch
    - subroutine or function call 
    - interrupt
    These modify the PC.  

    Perform requested task.
      Generally leaves results in ALU or pre-defined CPU work register.
      Saving results to memory required a separate instruction execution.
Done


* CPUs vary as to how handling of completed calculations, called write-back,
    is implemented.

    Some CPU designs allow this as a third operand. Common in RISC CPUs
      Add R2,R3,R1 ; add contents of R1 and R3 and store in R2

    Others implement this as a separate instruction.
      ADC $2043 ; Adds contents of memory $2043 to accumulator
      STA $2043 ; Write current accumulator to $2043

* RISC architectures usually fetch whole instruction (opcode and operand) in
    single fetch.

Initialize Program Counter (PC) to start address of program in memory.

While running
Do
  Address memory and fetch instruction from memory into instruction register. 

    Increment PC

  Decode instruction's opcode to determine task.

  Execute Task.
    In RISC, all calculations or other complex tasks occur between registers
      it the CPU.

    The one exception is a straight read from or write to memory.
 
  Writeback.
    In RISC, an instruction may specify 0, 1, or 2 register sources for 
      data and 1 target register for results of execution. Writing data
      to target register is the writeback step.

    Although treated as separate step, writeback completed in same clock cycle
      as the rest of the instruction.
 
Done 

* Newer CPUs, with wider buses, may fetch multiple instructions, implement
    pipelining and may even attempt parallel execution of instructions.


A simplified generic version of the fetch-execute (good test question) :


While running
  Fetch opcode

  Increment program counter (PC)

  Decode opcode 

  While operands needed
    Fetch operand

    Increment PC
  
  Endwhile

  Execute instruction

Endwhile