Reading : Instruction cycle

The basic fetch and execute cycle of a von Neumann or stored program computer.

  Key feature - memory holds both instructions and data.

  Instruction pointer (program counter) indicates location of instruction.

An instruction consists two parts :
  Opcode - indicates what task is to be performed.

  Operand[s] - indicates source of data to be acted on is 
               and where results stored.


Program counter (PC) - incrementing pointer may occur immediately after 
    fetch of instruction (during execution). More common.

  Or after instruction completion and just before fetch of next instruction.

  Exact implementation depends on CPU design.

Memory Address Register (MAR) - holds address of external memory being 
  referenced. Interfaces with the external address bus or CPU cache.

  Always written by the CPU.

  Harvard architecture has one for code and one for data.

Memory Data Register (MDR) - holds data being read/written. Bi-directional.
  Occasionally referenced as memory buffer register or MBR 

  Harvard architecture has one for code and one for data.

Instruction Register (IR) - register that holds current instruction being
  executed. This is the register the instruction decoder is reading.

Control Unit (CU) - circuity that decodes the instruction in the IR. 
  Complexity varies greatly between architecures.

  RISC - simple, fast, very few or no stages.

  CISC - complex, multi-staged, may be reprogrammable.

Arithmetic Logic Unit (ALU) - performs mathematical and logical operations.
  Usually only integer based and variety of operations vary greatly between
  CPU designs. 

Floating Point Unit (FPU) - performs more advanced floating point operations.
  Optional?

* Graphics Processor (GPU) - performs operations including floating point 
  operations required for advanced graphics. 

  In modern systems, the GPU has replaced the FPU. 

  In supercomputers, the GPU is not attached to a video display 
    but is used purely for its computational power.