How fetch/execute cycle processes a short assembler program:

The Program (6502 assembler):

0100 9a 23    lda #23    Load the byte value 23h into the accumulator
0102 8a 43 20 adc $2043  Add the byte of data found at memory 2043h
                         Also add one if carry flag set
0105 84 44 20 sta $2044  Store at memory 2044h


The Fetch/Execute sequence

# IP instruction pointer and PC program counter same. 

PC = 0100     (lda #23 instruction  2 cycles)
  MAR<-PC     Place PC contents on address bus, signal read required.
  MBR<-M[MAR] Read opcode = 9a into data register from memory.
  PC<-PC+1    Increment PC. PC = 0101  
  IR<-MBR     Move opcode to instruction register.
              Decode opcode - indicates that operand is needed.

PC = 0101  
  MAR<-PC     Place PC contents on address bus, signal read required.
  MBR<-M[MAR] Fetch byte = 23 into data register.
  PC<-PC+1    Increment PC. PC = 0102  
  AC<-MBR     Move byte into accumulator.


PC = 0102     (adc $2043 instruction  4 cycles)
  MAR<-PC     Place PC contents on address bus, signal read required.
  MBR<-M[MAR] Read opcode = 8a into data register from memory.
  PC<-PC+1    Increment PC. PC = 0103  
  IR<-MBR     Move opcode to instruction register.
              Decode opcode - indicates that next 2 bytes in memory 
              are the address of the needed data.

PC = 0103  
  MAR<-PC     Place PC contents on address bus, signal read required.
  MBR<-M[MAR] Fetch byte = 43 into data register.
  PC<-PC+1    Increment PC. PC = 0104  
  TL<-MBR     Move retrieved data into lower half of a double width 
              temporary register.

PC = 0104  
  MAR<-PC     Place PC contents on address bus, signal read required.
  MBR<-M[MAR] Fetch byte = 20 into data register.
  PC<-PC+1    Increment PC. PC = 0105  
  TH<-MBR     Move retrieved data into upper half of a double width 
              temporary register.
              Signal read.
  MAR<-TH/TL  Move combined address to memory address register.
  MBR<-M[MAR] Fetch byte at memory 2043 into data register.
  AC<-AC+MBR  Add data to Accumulator
  AC<-AC+CC[carry bit] Add carry if set.
  Change CC   Set carry flag if value overflows storage.


PC = 0105     (sta $2044 instruction  4 cycles)
  MAR<-PC     Place PC contents on address bus, signal read required.
  MBR<-M[MAR] Fetch byte = 84 into data register.
  PC<-PC+1    Increment PC. PC = 0106  
  IR<-MBR     Move opcode to instruction register.
              Decode opcode - indicates that next 2 bytes in memory 
              are the address of the needed data.

PC = 0106  
  MAR<-PC     Place PC contents on address bus, signal read required.
  MBR<-M[MAR] Fetch byte = 44 into data register.
  PC<-PC+1    Increment PC. PC = 0107  
  TL<-MBR     Store in lower half of a double width temporary register.

PC = 0107  
  MAR<-PC     Place PC contents on address bus, signal read required.
  MBR<-M[MAR] Fetch byte = 20 into data register.
  PC<-PC+1    Increment PC. PC = 0108  
  TH<-MBR     Store data in upper half of temporary register
  MAR<-TH/TL  Move combined address to memory address register.
  MBR<-AC     Move data from accumulator to data register.
              Signal a write.

PC = 0108   
              Place the PC on the address bus and signal a read. ...