ARM is an CPU design engineering company. They don't manufacture CPUs.
  They license designs/variations of their ARM architecture.

ARM - RISC, currently many versions used in a variety of devices.
 check out https://infocenter.arm.com
   Some pages freely accessible, others are only available if you
   register with ARM. (Should still be free).

ARM7 Family - 32 bit and 64 bit.
  ~ 600,000 transistors.

32-bit design. Full instruction fits in 32-bits.
   Allows 512 KiB direct addressing.

Fetch/Store only from memory.
  Register Indirect addressing used for full address range.

All data processing/manipulation done between registers.

Most instructions run in 1 clock cycle.
  But some versions have math or signal co-processors that
    function in parallel.

Supports AMBA (advanced micro-controller bus architecture)
  SOC - system on a chip.


Early designs did not support user level multi-tasking well.
(later models may, better accomplished with multiple cores)

Supports multiple modes.
 https://www.heyrick.co.uk/armwiki/Processor_modes
 USR - user task - application mode.
       Enforced  restrictions to privileged memory and instructions. 
 SYS - OS System mode - must be entered by command.
       * System mode can handle interrupt request by going to SVC mode.
       * Allows code to access memory that is protected.
 SVC - supervisor call. Hardware reset or software interrupt.
 ABT - abort issued after a code or data prefetch error.
       Privilege mode exception.
 UND - undefined instruction exception.
       Unrecognized instruction
       or one targeted for a co-processor not active.
 IRQ - Interrupt request.
       General interrupts such as reading keyboard.
 FIQ - Fast interrupt. Separate support to allow swift execution
       of some interrupts.
       Channel process or data transfer.
       Higher priority than IRQ.

 (Various ARM versions have additional modes).



Each mode recognizes
  15 "general purpose" visible registers.
   1 Program counter - R15
   1 current program status register (CPSR)

37 actual registers. 
  Multiple clones of R13, R14. FIQ has its own R8-R12
  R1-R7 shared by all modes.
  R8-R12 shared be all except FIQ
  R15 shared by all modes.
  Separate saved processor status registers (SPSR) for each mode.
    When a mode, other than user, is entered,
      the current processor status register (CPSR)
      is stored in that mode's SPSR.

Original design did not support multiple concurrent user tasks.

Registers

R0 - R12 GPR shared between most modes.
  * except R8 - R12, in FIQ mode - used for banking other registers.
     Banking refers to working with multiple copies of R13,R14.

SP (R13) stack pointer.
  Each mode except System has its own copy.
  With care, R13 can also be used as a GPR. However, if source code is
  C/C++, assume this will be used as a Stack pointer.

LR (R14) link register. Can be use to hold return address of subroutine
  that does NOT make any other subroutine calls (leaf).
    Rather than pushing return address on stack. 
  Each mode except System has its own copy.
  With care, R14 can also be used as a GPR.

PC (R15) - program counter. Shared.

CPSR - application or current program status register.

SPSR - Saved-PSR : own copies in svc, abt, und, irq, fiq. 
  Each mode, except system and user, preserves current state of CSPR 
    when interrupted.

CPSR(32-bit) condition codes.
  flags (arithmetic logic flags - zero, negative, carry, overflow )
    N(31) - negative/less than
    Z(30) - zero
    C(29) - carry/borrow/extend
    V(28) - overflow
    Q(27) - underflow/saturation, used to interface with support processors.

  IT1:0 (26,25) along with IT7:2(15-10) for instruction test if/then.
    Most instructions have an embedded if feature. (4 bits)

  J-bit(24) ARM/THUMB or Jazelle-DBX/Thumb2-EE
    Processor state (ARM, Thumb, etc.)
      Several current ARM processors can be run in 32-bit standard mode,
      16-bit Thumb mode for denser coding,
      hybrid Thumb-2 16/32 bit mixed mode.
      or directly execute execute Java byte code.
      * not all states available on all "models".

  23-20 reserved.

  GE[3:0](19-16) Greater/equal, used by SIMD instructions.
    * not available on all "models".

  E(9) Endian state - is data stored in little-endian or big-endian.

  A(8) disables imprecise abort.
  IRQ(7) disables interrupt.
  FIQ(6) disable fast interrupt.
  T(5) - state (normal/THUMB), combined with J bit.

  M[0:4](0-4) Mode bits selects mode register set.
  Current processor mode (svc, usr, irq, fiq, etc.)

All instructions 32 bits.
  4-bit condition filter. Provides for 16 test conditions including
    always. Exists on most instructions.

     Equal, Not Equal, Carry Set, Carry Clear, Negative, Positive or Zero,
     Overflow, No Overflow, Greater/equal, Greater, Less/equal, Less, Always.

  Op-code 3-8 bits wide. 
    64 instructions. Instruction also has conditional flags. 

  Fetch/store instructions use a register and
    either a 15 bit direct @
      * because bus is 32 bit(4-byte), actual range 2^(15+4) or 512 K

    or register holding a 32-bit address (full address range).
      Register indirect (pointer).

  All other actions done between named registers.

*
Three models
  Application - most complex.
    - handhelds, iPads, Kindles, iPods, MP3 players, etc.

  Real-time - fastest.
    - micro-controller for critical systems, e.g car emission controls.
    - supports a large number of interrupts.

  Micro controller - lowest cost, scaled back, more task specific.
    - but often includes a function specific co-processor.
    - used for multimedia, video processing, signal processing.
    - doesn't have the Thumb-2 or Java mode.

ARM 7 - von Neumann architecture
ARM 9 - Harvard architecture (implemented in cache(?))

Models capable of up to 1000 MIPS

3, 5, 15(latest - application model) stage pipeline models.

Most RISC chips are complete computers or SoC - system on chip.
 Features available - not all available on all models.

  AMBA - advanced micro-controller bus architecture (on-chip).
    Designed for co-processor environments.
  I/O circuitry.
  Video processing.
  Math co-processors.
  DSP - Digital Signal Processing - Analog to digital conversion.
  Configurable cache size/use.
  External memory access.
  On-board debugging system.

Modes available on various newer architectures.
Thumb mode
  16 bit alternative instruction set.
    Only GPRs R0-R7
      and R13, R14, and R15 available
    Runs 30% faster.
    Code size reduced by 30%

Thumb-2 mode
  Mixed 16/32 bit instructions.

Jazelle-Java
  Can decode and execute Java byte-code directly.

Secure Code
  Smart card models.
  Supports/incorporates cryptographic co-processor.

Instruction types.
   Signed branch/branch with link (subroutine call)  +/-32MB (16-bit)
     * with link will use R14 for return address.
     * Compiler has ways to extend branch past +/-32MB
       by adding additional code.