Conventional PCI Designed for burst transactions. Controller acts as a system address decoder for any devices interfaced with it. On power up/configuration , controller probes its interfaces and negotiates connectivity. It also negotiates with the system/device drivers to identify what it found. All system/PCI activity passes through the PCI controller. Controller arbitrates bus mastering. Device requesting bus control is the initiator. Initiator then contacts 'target'. Data transferred in transactions. A transaction consists of an address and command transfer followed by zero or more data transfers between initiator and target. Initiator signals address of target on data bus, indicates type of activity with C/BE lines, and pulls FRAME low. Devices must latch target address on 1st clock. Target may take up to 3 clock cycles to respond by asserting DEVSEL. It has an additional 3 clocks to latch and process request. If initiator and target in agreement. Burst transfer - sequentially send data until done or condition causes termination. Each transfer may take up to 8 clock cycles. Very small data transfers 'expensive' because of setup overhead. C/BE used to limit/identify the bytes of data on the 4-byte wide bus. Transaction size is unbounded. Although real world tends to limit this. Transactions are unidirectional but may be either way. Transactions cannot be interleaved. Transaction can be suspended but requires renegotiation to restart. Note - transaction is not the same as a packet. 32-bit multiplexed data/address bi-directional bus. 4-bit C/BE - command, byte enable(mask) In address phase, indicates type of transaction. In data phase, acts as a mask if not all 4 bytes of 32-bit bus needed. Variety of control lines. 4 device shared bus signal must be able to drive 4 interfaces. All interface logic follows strict timing and signalling specs.. Also sets limit to maximum speed/throughput. 33 MHz x 32-bits ~ 120-150 MB/s (after overhead) # there are 66 MHz and 64-bit versions but fairly rare. Bridging allows more interfaces. But bridging interface 'smarr' and has to handle arbitration. Bus provides 4 isolated REQ/GRT arbitration signal pairs, one per slot. Bus provides 4 shared (round robin) interrupt request lines. Device may use more than one. Device driver expected to help resolve requests.