IEEE 488

Controller sets up communication between talker and listener using data 
  lines for addressing combined with control lines, such as ATN.
  
  Most often controller is also either the talker or the listener, but does
  not have to be.

While talker not indicating end of transaction 
Do
  Talker indicates data invalid (new transaction).

  Talker waits for listeners to finish any current data processing

  Talker puts data on data lines.

  Listeners notice data and acknowledge data exists.
  
  When Talker sees listeners listening, it indicates new data is valid.

  Each listener indicates it has grabbed the data.
    Listeners must latch data.
    Only targeted listener does anything with the data.
 
  When all listeners indicate data accepted, talker indicates data invalid and 
    process starts over for next byte of data.
  
  * Protocol delivers 1 byte at slowest device's response speed.
Done

*****************

PCI 

Arbiter - bus controller.

Initiator - any device driving the transmission of data, data may move either
  way.

Target - device being communicated to.

* 

Initiator requests permission to master bus using various control lines in 
order to perform a transaction.

Arbiter "grants" permission to initiator. As long as a grant is in effect the
  initiator may do multiple transactions among various targets. But, it can
  only work on one transaction at a time.

* address phase

Initiator asserts it is starting a frame of data.

Initiator puts a target address on data lines (32 bit) and a command on the 
  command lines (4 bit) to indicate the type of address, memory, i/o, 
  configuration, and task being performed, read, write, burst mode, etc.

Targets are given 3 clock cycles to receive and latch address and command.

Any device may have up to 3 address ranges assigned to it.

The addressed device has an additional 3 clocks to acknowledges it has been 
  addressed using the devsel line to reply.

If after 6 clock cycles no one responds, initiator aborts transaction.

If all is good, initiator asserts a ready to transmit data.

* data phase

Initiator uses the 4-bit command lines to mask the 4 byte data bus. PCI allows
  0 to 4 bytes to be transferred at a time. A NOP transmission is valid.
  A NOP allows initiator to stall data transmission for a short time without
   giving up control of the bus if the target is slow.

Data can be transfered in either direction but only in one direction for the
  current task.

Once data starts transferring, it transfers at the bus clock speed unless 
  initiator or target indicate it is not ready any more.

When one of the devices is no longer ready, that data phase is done. 
  Signalled with IRDY or TRDY.

  Some reasons : 
    All data sent.
    Sender may be waiting for something else to provide more data.
    Receiver's buffers may be full.
    Error conditon occurred. 
    
*

Controller can grant mastering to more than one initiator as long as they
are not attempting to communicate over the same bus.

*

There is a fair amount of overhead in initiating a transaction but some 
devices can burst large blocks of data once the transaction is initiating.

Note that this is similar to the IEEE 488 bus. The difference is that without
timing, handshaking occurs for each byte. With PCI, once the virtual connection
is established, the data can be pushed at the clock speed until complete or 
a device indicates a need to stop.