ISA Industrial Standard Architecture bus.
  Extension of the Intel CPU's bus pin-out.

  Single-ended signaling.

  XT-1981 (4.7 MHz)  AT-1984   Generally obsolete late 90's

  Data bus
    XT : 8 bit   
    AT : 16 bit 

  Address bus
    XT : 20 bit
    AT : 24 bit

  Address and data multiplexed on XT but not AT.

  6 or 8 MHz matching 30286 CPU (XT - 4.7 MHz 8088/6)

  Original clock speed was tightly coupled to memory response 
    However AT speeds required addition of waits handled by memory controller.

  Provided interface slots that made most of the address, data, and 
    control lines available to any add-on device.

  98 pin (XT - 62 pin) connections.

  Interface slots were expanded but were backwards compatible.
    ============= ======
    XT            AT extensions

  XT - 6 of 8 interrupt lines (2 reserved - not on bus).
  AT - Additional 7 interrupts. (only accessible via the extension slot)

  Clock Finalized at 8.33 MHz   Capable of up to 8.33MB/sec transfer.

  -5 Volt for electronic interface circuitry.

  +/- 12 Volt to drive mechanical devices and serial i/o.
    In practice, most devices draw power directly from power supply.

  Multiple ground lines.

  Reset

  4 DRQ and 4 DACK - 4 pair DMA handling signals.
    DMA 0 reserved for memory and does not show up on expansion connectors.
    DMA 2 assigned to Floppy (BIOS supported)
    DMA 3 assigned to Hard drive controller. (BIOS supported)
    DMA 1 for user cards.
      If shared, software drivers did additional arbitration negotiation.

  Memory and I/O data direction lines.

  Interrupts and DMA support mostly jumper (hard-wire) based.
    And recognized by drivers, bios, and CMOS.

    Interrupts 0 and 1 wired directly to special logic, not seen on bus.
      Remaining interrupts available but often pre-assigned in bios to 
        specific tasks/devices such had hard drive, floppy, serial i/o, etc.  

    * CPU only received one interrupt. It then communicated with an external
      circuit which reported id of device requesting IRQ.

  I/O ready and check lines.

  Design of system expandable.  
    CPU and memory on mother board, all other functions on expansion cards.
  
  Although proprietary, IBM never really enforced its ownership. 

  Later AT extension added more address, data, and interrupts while still
    allowing older cards to work.

  As CPUs got faster, additional buffering and/or tiered control circuits
    used to interface CPU to bus.

  A variation of the ISA bus is still implemented in embedded system 
    environments. 

  Supported a very limited amount of PnP (plug-n-play), but most configuration
    done with hardware jumpers and CMOS settings.

  Still used in industry for controllers
    Low speed acceptable and is more immune to noise than current buses.