Buses occur at several levels in a system.
The CPU has an internal bus.
The system as a whole has a bus system to allow all of the parts to interact in a coordinated manor.
And on modern systems, groups of components may have dedicated buses to allow them to interact with among themselves without the intervention of the CPU.
An example of bus usage
Buses in general
Early systems used a single integrated system bus. This simplified the design but meant that the slowest component affected the whole.
New systems have several custom busses with buffered interfaces. These allow each sub-bus to run at its optimal speed, often without interaction with the CPU.
Buses are describe by a published protocol. This protocol guarantees that any user of a particular bus knows its properties and behavior and can design components to take advantage of those properties.
| Omnibus PDP-8 | Unibus PDP-11 | Multibus 8086 |
| S100 - Technical instruments, mini-computers | IEEE-448 - Parallel Peripheral Interface | IBM PC(PC/XT) |
| ISA (XT/AT) | EISA (80386) Faster/wider than ISA | Micro-Channel (PS/2) - proprietary competitor to EISA |
| PCI(PCs) | SCSI - Small computer systems interface | NUBUS( MacIntosh) |
| USB (PC Intel) Serial, daisy chained devices. | Fire-Wire ( Consumer Electronics, Mac, Some Intel PCs) |
A bus is non or bi-directional. The nature of the devices or units accessing the bus determine the direction in which data flows.
Devices on a bus are called masters if they can initiate an action on the bus. And Slaves if they are passive and respond. Some devices are designed to function in either mode or in both.
However, at any one time, there can be only one master.
Additionally, a device may be isolated electrically from the bus using a tri-state-state latch which allows a device to appear as if it were not there.
Bus vs port
A port is generally considered a connection between only two devices. At the simplest, it consists of 1 data line, minimal control and no address. Serial port.
However, many current ports have most, if not all of the features of a bus. Multiple bi-directional data lines, some addressing, and complex controls. For example, the current parallel port standards, with the support of software drivers, allows the system to ask the device attached to identify itself. Additionally, some devices are designed to allow pass through connections, such as zip drives, thus allowing a second device to function on a single port.
In general, a bus is used to connect multiple devices, with the devices and not the bus determining overall control.
Bus complexities.
A bus has two major properties, the number of lines and the speed at which it functions.
By increasing each of these, the overall throughput of the bus is increased. However, each also comes at a cost.
The more lines a bus contains the more complex the implementation, both in complexity and in overall real estate.
Increasing speed creates various problems. The quality of all components must increase. Additionally, property called skew occurs. As the various signals and data are propagated across the system, they do not all take the same path. Some take physically longer paths, other have to pass through additional circuitry. Each of these increase the time delay for the particular signal.
Most systems attempt to function in a synchronous manner for most their tasks. This means that certain things will be done at certain times or during certain windows of opportunity usually indicated by the system clock.
As the speed of the bus gets faster, these windows get smaller. If a particular action requires the interaction of several signals and one of these signals is late, then either the action is aborted or the system must wait until the next window opens (wait on memory).
Another feature of the bus that affects its behavior is whether its devices function synchronously or asynchronously.
In synchronous mode, a system clock marks a beat and interaction functions in step with that beat with responses occurring at predicted times. This makes for a simple bus implementation and interaction but requires better design of the units. Cache, s-dram, and video memory.
In asynchronous mode, the different module function independently and then signal when they want to interact. This allows the modules more freedom but requires that the bus and its support hardware be able to support and acknowledge these interaction requests. Printers, keyboards.
Most modern systems support both modes because of the wide variety of devices available.
The four main sub-categories of bus architecture are address, data, control, and power. In general, these are distinct and straight forward. However, this is not always true.
On early CPUs, it was common to allow the pins of the CPU to perform two different functions depending on the state of the clock. For example, the Intel 8086 could address 1 M (20 bits) of 16 bit memory. It also requires 1 power input, 1 ground, the clock input, r/w signal, reset, i/o select (42+), etc.
However, it was produced in a 40 pin package. This meant that many of the pins and the physical bus had multiple functions. The support circuitry was designed to split apart the function of the bus outside the CPU based on either a specific control signal from the CPU or on whether the system clock was going from 1 to 0 or 0 to 1.
A different example is found when addressing memory. A CPU may be able to access a large address range. However, individual memory modules are not designed to span this full range and cannot recognize all possible addresses. Suppose you have a system with 2 128M memory modules. Each module is physically identical, meaning that each can recognize addresses 0 to 2^27-1. So how does a particular chip know when it is being accessed?
This is done by using address pin 28 in combination with various control signals such as address ready to select the memory chip. Now the question is: Is a28 a control signal or has the ready signal become an address signal?
Address bus
The address bus is used by the master circuit, usually the CPU, to contact and activate the other circuits and logic units, such as memory, video cards, etc., found in the system. The bus generally contains all the address lines needed to address the full address range recognized by the CPU.
Some of the new CPUs are capable of addressing 4 Gig of memory or greater. Since placing that much memory on a system board is both economically expensive and physically difficult, memory slots may not be tied to the high end address lines.
Data placed on the address bus always originates from the CPU or other master circuit.
Data bus
The data bus is to pass "user" data between various circuits in the system. It is bi-directional in nature with various control lines indicating the intended direction.
Control bus
Various Controls
Transfer Request/ACK - address ready, wait
Bus direction control - R/W direction, Memory, I/O
Interrupt Request/ACK - used by i/o to get the CPU's attention.
Bus Request/Grant (arbitration) - regulate access to the bus by various devices, such as sub-bus systems, storage devices, and the CPU, Co-processor signals, FPU or Video card.
Status - provide or accept status such as r/w success.
Clock
Misc - reset request.
Data direction - direction data is moving between master and slave.
Memory / I/O - Determines whether memory being accessed or an i/o device. Some systems do not recognize i/o devices but rather treats them as another memory location. This means the i/od device must be able to handle some of the responsibility of the CPU.
Bus arbitration - If multiple masters exist on the bus, a traffic cop must exist to guard against 2 devices attempting to assert mastery at the same time. This may include having a priority system in existence.
Interrupt handling. Because many devices function asynchronously, such as keyboard, printers, and disk drives, a system must exist to check on these devices and service them when needed.
One way is a system called poling in which the CPU or some device, constantly or on a small enough interval, checks the status of each device for service. While simple to implement, it tends to be wasteful of computing resources.
An alternative is to allow the device to request an interrupt of the normal system procedures when service is required. A request for a file is made to a disk, but the disk has to spin up to speed and find the appropriate sectors. So the request is made and the CPU goes on to perform some other activities. When the disk has found the data and buffered the first block, it requests an interrupt of the CPU's current activities. In the case of the disk drive, once the data has been found, it is better if all the data is read in quickly. The CPU stops what it is doing (remembering its place) and handles the first block of data. If the next block is not ready, it can go back to what it is doing until the disk is ready with the next block.
Interrupt requests come in two flavors. Regular (IRQ) and non-maskable (NMI).
Regular interrupt requests can be ignored by the CPU. For example if two different reads have been requested and the first read is being processed, it is not practical to stop if the second read indicates it is ready, so it is ignored until the 1st is done.
Interrupts are also assigned priorities. Both the disk read and the keyboard read are interrupt driven but have different priorities. If a disk indicates it is ready for a read while the user is typing in data, the user will probably see the keyboard hang. And if the user attempts to enter data after a read has started, the same effect will occur because the disk read has a higher priority than the keyboard read.
Although interrupts can be generated from any number of devices, these interrupts are usually routed to a central device that is capable of handing the priorities and masking before passing the IRQ on to the CPU.
Non-maskable interrupts tend to be catastrophic, such as memory errors or imminent power loss, they cannot be blocked and have higher priority than IRQ.
Signal (acknowledgment) - Associated with memory access, bus mastering, and interrupts. This is the response signals to the requests generated by the other control signals.
Clock - the clock provides the synchronization of the system.
Misc - reset request. All systems come with a reset signal. This signal is capable of bringing the CPU up into a default state without killing the power to restart the system. It is made available to users on most systems. It is also used to hold the CPU at the default state on power-up while all of the other devices become active. The default state will include the initial Instruction pointer value and status flags. On 80x86, this is ffff0
Data bus
Finally, power and ground are supplied by a separate set of lines. Generally, power is supplied at two levels.