Bus
  The bus is used to connect the components of the system.

  Provides an I/O path between the CPU and the world.

  Follows a protocol to provide predictable behavior.

  An I/O device (disk, keyboard) requires a controller and
    the device itself.

  The controller in turn is connected to the CPU via a bus.

Bus protocols.
  Properties of a bus are laid out by their protocol.

  A protocol is a description of the properties of a system
    or device.

  Published protocols allow manufacturers to build new devices
    that will correctly work with a system.

  Some systems use a proprietary bus.

Bus categories  -  Four sub-types.
  Power - used to provide power to the various components.

  Address - used by master to select a slave to interact with.

  Data - used to transfer data between master and slave
    (bi-directional).

  Control - used to guarantee correct interaction of components.
    Timing - synchronization of components.
    Interrupt - service request from slave component.
    Arbitration - access negotiation when there is more than 1 master.
    Data direction - indicate direction of data transfer (to or from master).
    Status/Acknowledgment - reports and notes status of a component.

Protocol specifics include:
  Number of lines for each of the sub-categories.
  Speed of the bus lines.
  Types of control available.
  Voltage levels.
  Timing limits.
  Physical layout of the controller/bus interface.

Buses
  XT and AT (PC) bus - original bus for the IBM PC.

  ISA (Industry Standard Architecture) - generic version of PC bus.

  EISA (Extended) - wider data bus, improved speed and control.

  MCA (Micro-channel architecture) - wider bus, improved speed and control.
       (Proprietary - required licensing from IBM).

  PCI (Peripheral Component Interconnect) - wider, faster, greatly
       improved control. Protocol public but Intel manufactures most of
       the logic chips needed to make it work.

  AGP (modified PCI) - used to connect a small number of time/data
       critical devices.

Bus - used to connect logic units or devices.
  Internal to CPU.
  Between CPU and other logic circuits or peripheral interfaces.
  Between computer and external devices.

Ports and Buses
  Bus - used to connect multiple devices with a single set of lines.
    Must provide facilities to distinguish devices (addressing).
    Must provide sufficient controls to ensure proper functioning.
    Must provide bi-directional data movement.
    Support circuitry independent of devices using it.

  Port (interface) - used to connect a single device to the system.
    Addressing often not supported.
    Minimal controls.
    May provide only uni-directional data movement.
    Port interface responsible for controlling port lines (master).

Ports
  Serial - sends one bit at a time and may have up to 8 control lines.
  IEEE 448 - parallel port protocol (technical devices).
    handles multiple devices and bi-directional.
  Parallel printer
    Centronics - original PC printer connection. Unidirectional.
    IEEE 1284 - major upgrade of Centronics.

Parallel
  Legacy parallel "Centronics" port. (SPP)
  4 control lines
  5 status lines
  8 uni-directional data lines
  8 ground lines
  150 kilobytes/sec

SPP improvements
  Reverse - has to be supported by software.
    Nibble mode - 4 bit reverse data transfer using status lines for data
       transfer. Supportable with "Centronics" ports.

    Byte mode - Hardware manufacturers redesigned ports to allow software 
       to disable the data output driver circuits and reverse data direction. 
       Late model "Centronics" ports.
    
Bidirectional EPP
  EPP - Enhanced parallel port (Pre 1284)
    Four modes of data transfer
      Data write cycle
      Data read cycle
      Address write cycle
      Address read cycle
        Addresses
        Channel - distinguish function in a fax/modem/printer
        Commands
        Control.

    Mixed hardware & software support.
    
IEEE 1284 - bidirectional ECP
  ECP - extended capacity port
  Supports addressing, bidirectional data transfers, channels, commands, 
    status.
  Can access printer and modem simultaneously.
  Controllers has dedicated registers for the various functions.

IEEE 1284
  Current systems support IEEE 1284 parallel port.
  Usually CMOS configured.
  > 1 MB/sec
  5 modes
    Forward direction.
      Compatibility mode - "Centronics" - forward direction only.

    Reverse.
      Nibble mode.
      Byte mode.

    Bi-directional
      EPP (slight improvement over original).
      ECP

Bus issues
  Bus - a set of real or virtual lines that connect a system's units.
    Real - several separate lines for power, data, address, control.
    Virtual - a limited set of lines used for multiple purposes.

  Bus shortcomings.
    Latency - any delay between issuing an action and the completion. In 
       a bus - delay that occurs because of distance and intermediate gates.

    Propagation delay - an accumulating delay caused when a signal must 
       pass through a gate.

    Skew - signals traveling in a set of lines will arrive at destination 
       at different times because lines will not have identical lengths.

    Attenuation - the loss of the strength of a signal as it travels. 
       Digital signals tend to round, flatten, and spread.

Speed and Distance
  Bus short comings are amplified by two factors.

  A signal travels approx. 1 foot in 1 ns. 

  1 MHZ = 1000 ns, 100 MHZ = 10ns, 1 GHz = 1ns. 

  Speed - faster signal changes (higher data speeds) cause skew, 
     propagation delays and latency to become more obvious.

  Distance - greater distances cause shew, latency, and attenuation.

Bus classes
  Synchronous bus 
    Clock is provided to signal to all devices when a valid information 
       transfer can occur (@, data, control).
    Simplifies control and interaction between devices.
    Requires that devices function a defined synchronous order.

  Asynchronous bus
    No clock.
    Additional control signals needed to guarantee proper interaction.
    Devices interact only when and if necessary.
    Timing information often embedded in data (lowers data throughput).

Control bus
  Control bus provides a variety of signals that provide for proper 
     interaction of units.

  Common controls (not all found on all systems).
    Data direction - specified the direction of data movement between master
      and slave.

    Memory/IO - indicates whether address specified identifies primary
       memory or an I/O device.

    Bus arbitration (request/grant)- provides correct interaction on
       multi-master systems.

    Status - used by slave units to indicate their current state or 
       acknowledge an action by master.

    Interrupt - used to request the attention from master.

    Clock - provides for synchronization of system.

    Misc - example - reset - causes the system to reboot. 

Interrupts
  Interrupts are used by a client (slave) device to request attention 
     and action from the master (CPU) unit.

  Interrupts are generally prioritized.
    An attention request from a hard drive is more time sensitive than 
       one from a keyboard.

  Priority of interrupts are often handled by a dedicated circuit which 
     delivers a general interrupt request to the master with enough data to 
     determine interrupt source.

  Interrupts come in two forms
    Standard or mask-able (IRQ)
    Non-mask-able

Interrupts
  Mask-able or plain interrupts. (IRQ) 
    Represents conditions that affect activity but not system integrity.
      can be ignored.
      can be delayed.
      can be processed.

  Non-mask-able. (NMI)
    must be processed (usually represent catastrophic condition).
      generated by software.
        invalid commands.
        illegal memory accesses.

      generated by hardware.
        hardware failure.
        real time critical data transfers.