Arch.ModelSpeedRegisters Address
Bus		 Data
Bus		 Instruction
Count
Mos 650x 6502 1 Mhz 1 8-bit A (accumulator)
2 8-bit (X,Y) index registers
- counters, and address indexing
16-bit Instruction Pointer
8-bit Stack Pointer 		16-bit 8-bit
Intel x86 8088 4.7MHz 16-bit AX (Accumulator)
16-bit BX (Base) - used for memory addressing
16-bit CX (Counter) - used as loop counter
16-bit DX - used with A for integer math > 16-bit
A,B,C,D can be address as h,l half registers

16-bit SI, DI - Index pointers used with B for addressing
16-bit SP (Stack Pointer)
16-bit BP (Base Pointer) - secondary pointer fo stack access
16-bit IP (Instruction pointer)

16-bit CS (Code segment pointer) paired with IP to get 20-bit @
16-bit DS (Data segment pointer) paired with SI to get 20-bit @
16-bit ES (Data segment pointer) paired with DI to get 20-bit @
16-bit SS (Stack segment pointer) paired with SP to get 20-bit @
16-bit CC (condition code)

    Z - zero, N - negative, V - overflow, I - interrupt mask,
    T - trap, D - decimal adj.

 20-bit8-bit
80868 MHz
10 MHz		 Same registers 20-bit 8-bit
ARM ARM 7 Models
    A Application
    R Real-time
    M Microcontroler (embedded)
4-110 MHz common
800 MHz available		 37 32-bit registers - 16 visible
    von Neumann architecture

    R0-R12 - user registers
    R13 - Stack pointer
    R14 - Link (return address for subroutine call)
    R15 - PC (Program counter)
    * multiple copies of R13,R14 for preservation during exception

CPSR - Current program status register

SPSR - stored current program status (exception mode)

Non-visible used for exception(interrupt) handling

Status register (part of CPSR)

    4 condition codes, Negative, Zero, Carry, oVerflow
    2 interrupt disable bits
    4 GE (greater or equal flag, some ARM cpus)
    1 Imprecise Abort Mask (ARM 6)
    5-bit processor mode
    2-bit instruction type
    1 endian flag
6-8 modes, some make use of
the additional registers
    User - most applications
    FIQ - Fast interrupt request
    IRQ - Interrupt request
    SVC - OS protected mode
    Undef - handles bad code
    Abort - handles bad memory accesses
    * System - OS privileged user mode
    * Monitor - TrustZone mode (secure)

Some versions support Thumb mode
16-bit, smaller faster code

32-bit 32-bit Variable length
opcode 3-7 bits

Most instructions
have conditional bits

ARMARM 9
Application
model		 1000-2000 MHz available Harvard architecture

 32-bit
64-bit (ARM8A)		 32-bit
64-bit