Given a CPU data-path of a certain stated timing design, be able to determine Given a CPU running at a certain clock rate, and a description of the timing of an instruction as it passes through the stages of the data path,

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Given a memory address and a certain cache configuration, determine the segment ID, the line number where it will be cached and the byte offset into the line where the target byte is. See Worksheet and key for best example. Given an actual cache and a program that performs a series of memory accesses, be able to show contents of the cache as the program executes for direct and 2-way set associative.

The following pages contain links to example caches :

Direct     Direct example

N-way     2-way example

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Associative and set associative caches provide an improved alternative to direct caching. They allow data to be mapped to one of several alternative lines in the cache. However, if cache is full, you must choose which cache line to free.

Name (full name, not just abbreviation) three mechanisms/rules that can be used to select the cache to replace.

Line selection