CSCI 463 Test 3 example Spring 2018   Z-Id ________  Name ______________________

Pipelining. Given a cpu running at 300 MHz, assume there are no read competition
between each stage of instruction completion.

Design uses a 4 stage fetch/execute and clock for each stage listed :

Opcode fetch - 1 cycle,   decode - 1 cycle, Operand fetch - 3 cycles, execute - 5 cycles

Pay attention to CPU clock speed. And show units of measurement.

A. Give the time in clock/cycles to execute 1 instruction.



B. Give number of instructions per second if NON-pipelined.




C. Give number of instructions per second if pipelined.




D. Give number of instructions per second if the execution step is super-scalar.



(3) Set Associative Cache line selection. Name three alternative methods used by set
associative caching to select cache line to replaced when all target lines are in use.
Don't use abreviation.

a.


b.


c.


Parsing a memory address to detemine cache location.(6)

Address : 4 GB memory.  Cache configuration : 1024 lines, 8 bytes/line.

Calculate bit size of  Tag ID. ________   Line index _______   Byte index _______


Determine the tag, line index, and byte index of the Memory address : F3ABF

Value of               Tag ID. ________   Line index _______   Byte index _______