BUSx allows or provides for bus mastering.

BUSx has a dedicated clock line.

BUSx has separate pairs of unidirectional serial data connections(links), but only one of each.

BUSx interfaced logic can signal interrupt request an any time.

BUSx multiplexes address, data, and control over same lines.

BUSx supports burst mode transmission.

BUSx uses a single half duplex data link.

BUSx uses bit stuffing.

BUSx uses differential signaling on its data lines.

BUSx uses NRZ encoding.

BUSx uses NRZI encoding.

BUSx uses packet based communication.

BUSx uses reflected wave signaling on its data lines.

BUSx uses RLL encoding.

BUSx uses serial communication but supports multiple serial lanes, interleaving individual bytes on available lanes.

BUSx uses single-ended signaling for its data lines.