How fetch/execute cycle processes a short instruction sequence.

As C code :

  num1 = 35 + num1;


As 6502 assembler :

  0500   clc        Clear carry flag in CCR.
  0501   lda #23    Load the byte value 23h into the accumulator
  0503   adc $2043  Add the byte of data found at memory 2043h
                              Also add one if carry flag set
  0507   sta $2043  Store at memory 2043h


As 6502 machine code in memory :

   18 9a 23 8a 43 20 84 44 20 ..

   Note that 6502 uses little-endian, so adc $2043 is  8a 43 20


As von Neumann fetch/execute cycle :

  Examine Program counter for location of instruction
  Retrieve instruction opcode (clc - clear carry) from memory.
    Copy into the instruction decoder register.
    ----------------------------------------------------------
    |Place copy of Program counter in Memory address register.
    |Signal memory read.
    |Wait for memory to place instruction opcode on the data bus. 
    |   which is externally attached to the Memory data register.
    |Copy from memory data register into the instruction decoder register.
    ----------------------------------------------------------
  Increment Program counter to next memory unit.

  Decode instruction opcode (opcode indicates no opperands required)
  Execute instruction by clearing Carry bit in CCR.

  Examine Program counter for location of next instruction
  Retrieve instruction opcode (lda - load accumulator) from memory.
    Copy into the instruction decoder register.
  Increment Program counter to next memory unit.
 
  Decode instruction opcode  (opcode indicates it uses 1 byte operand)
  Fetch operand (#23) from memory.
    (Place address in MAR and wait for memory to respond on MBR)
  Increment Program counter to next memory unit.

  Execute instruction by copying the value found in the MDR (#23) into the 
    cpu's accumulator.


  Examine Program counter for location of next instruction
  Retrieve opcode of instruction (adc - add with carry) from memory.
    Copy into the instruction decoder register.
  Increment Program counter to next memory unit.

  Decode instruction  (opcode indicates it uses a 2 byte operand that
    indicates a memory location to read from)

  Fetch 1st byte of operand (#43) from memory and store in work register.
  Increment Program counter to next memory unit.

  Fetch 2nd byte of operand (#20) from memory and store in work register.
  Increment Program counter to next memory unit.

  Execute instruction by placing the address retrieved ($2043) on the MAR
    and retrieving the value returned in the MDR, adding it to the contents 
    of the accumulator, and if carry flag set, add an additional 1.


  Examine Program counter for location of instruction
  Fetch opcode of instruction (sto - store) from memory.
    Copy into the instruction decoder register.
  Increment Program counter to next memory unit.

  etc. ....
   

As fetch/execute cycle in a 6502 cpu :

PC - program counter             IR - instruction register
CC - condition code register     AC - accumulator
MAR - memory address register    MBR - memory buffer register
TL/TH - dual 8 bit temporary register.

The MBR may also be called MDR - memory data register.
The PC may also be called IP - instruction pointer.

The Fetch/Execute sequence

Fetch Step
  PC = 0500     (clc 1 cycle)
    MAR<-PC     Place PC contents on address bus, signal read required.
    MBR<-M[MAR] Read opcode = 18 into data register from memory.
    IR<-MBR     Move opcode to instruction register.
    PC<-PC+1    Increment PC. PC = 0501  
                  Some cpus use the alu to increment the PC which would
                  tie up the accumulator and add several steps.
                  Others have a separate dedicated PC adder.

                Decode opcode - indicates that operand is needed.

Execute Step
    CC[C]=0     Set carry flag of CCR to zero.
                N Z C I D V
                - - + - - -   

Fetch Step
  PC = 0501     (lda #23 instruction  2 cycles)
    MAR<-PC     Place PC contents on address bus, signal read required.
    MBR<-M[MAR] Read opcode = 9a into data register from memory.
    IR<-MBR     Move opcode to instruction register.
    PC<-PC+1    Increment PC. PC = 0502  

                Decode opcode - indicates that operand is needed.

  PC = 0502  
    MAR<-PC     Place PC contents on address bus, signal read required.
    MBR<-M[MAR] Fetch byte = 23 into data register.
    PC<-PC+1    Increment PC. PC = 0503  

Execute Step
    AC<-MBR     Move byte into accumulator. 
    Change CC   Set various flags as appropriate.
                N Z C I D V Negative and zero possibly affected.
                + + - - - -    

Fetch Step
  PC = 0503     (adc $2043 instruction  4 cycles)
    MAR<-PC     Place PC contents on address bus, signal read required.
    MBR<-M[MAR] Read opcode = 8a into data register from memory.
    IR<-MBR     Move opcode to instruction register.
    PC<-PC+1    Increment PC. PC = 0504  

                Decode opcode - next 2 bytes are address of needed data.

  PC = 0504  
    MAR<-PC     Place PC contents on address bus, signal read required.
    MBR<-M[MAR] Fetch byte = 43 into data register.
    TL<-MBR     Move retrieved data into lower half of 2 byte temp register.
    PC<-PC+1    Increment PC. PC = 0505  

  PC = 0505  
    MAR<-PC     Place PC contents on address bus, signal read required.
    MBR<-M[MAR] Fetch byte = 20 into data register.
    TH<-MBR     Move retrieved data into upper half of 2 byte temp register.
    PC<-PC+1    Increment PC. PC = 0506  

Execute Step
    MAR<-TH/TL  Move combined address to memory address register.
    MBR<-M[MAR] Fetch byte at memory 2043 into data register.
    AC<-AC+MBR  Add data to Accumulator
    AC<-AC+CC[c] Add carry if set.
                For 6502, programmer is responsible for setting initial value
                of carry register before performing math.

    Change CC   Set various flags as appropriate after completing both adds.
                N Z C I D V  Negative, zero, carry, and overflow affected.
                + + + - - + 

Fetch Step
  PC = 0506     (sta $2043 instruction  4 cycles)
    MAR<-PC     Place PC contents on address bus, signal read required.
    MBR<-M[MAR] Fetch byte = 84 into data register.
    IR<-MBR     Move opcode to instruction register.
    PC<-PC+1    Increment PC. PC = 0507  

                Decode opcode - next 2 bytes are address of needed data.

  PC = 0507  
    MAR<-PC     Place PC contents on address bus, signal read required.
    MBR<-M[MAR] Fetch byte = 44 into data register.
    TL<-MBR     Store in lower half of a double width temporary register.
    PC<-PC+1    Increment PC. PC = 0508  

  PC = 0508  
    MAR<-PC     Place PC contents on address bus, signal read required.
    MBR<-M[MAR] Fetch byte = 20 into data register.
    TH<-MBR     Store data in upper half of temporary register
    PC<-PC+1    Increment PC. PC = 0509  

Execute Step
    MAR<-TH/TL  Move combined address to memory address register.
    MBR<-AC     Move data from accumulator to data register.
                Signal a write.

Fetch Step
    PC = 0509   
                Place the PC on the address bus and signal a read. ...