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Example:

CISC runs a routine :

  simplest command        3 clock cycles 
  most complex command   16 clock cycles
  simple/complex         75/25

  75 * 3 + 25 * 16 = 625 clock cycles.


RISC runs a routine 

  all commands 2 clock cycles. 
  However, each complex instruction replaced by 12 RISC instructions.

  75 * 2 + 25 * 12 * 2 = 750 clock cycles.

The risc required an extra 125 clock cycles.


Suppose instead of a ratio of 75 simple to 25 complex instructions,
  it's 95 to 5.

  For the CISC system we have : 95 * 3 + 5 * 16 = 365 clock cycles.

  For the RISC system we have : 95 * 2 + 5 * 12 * 2 = 310 clock cycles.

  The risc required 55 fewer clock cycles.


With a ratio of 98 to 2

  For the CISC system we have : 98 * 3 + 2 * 16 = 326 clock cycles.

  For the RISC system we have : 98 * 2 + 2 * 12 * 2 = 244 clock cycles.

  The risc required 82 fewer clock cycles.


This is a small savings but if the system is running mostly programs 
with the 95/5 ratio or better and consisting of 1000s of such commands, this 
starts to accumulate.

When implemented with pipelining, the data hazard and structural hazards are 
  easier to avoid in a RISC architecture.

Simpler design can allow for faster overall clock speed.

Simpler design draws less power per clock cycle.

Cost of manufacturing RISC cpus can be significantly cheaper.


The question becomes:
  How often is a complex instruction actually called?

  On a Computer aided drafting system (CAD), often.

  On a Microwave, Cable remote, or even network router, never.