PCI-e

Peripheral Component Interconnect Express

check out : http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-1

The goal of PCIe is to implement the PCI bus over a set of point to point physical interfaces.

PCIe implements a serialized link layer onto the PCI bus.

Most of the conventional PCI protocol still implemented, but some has been udpate or replaced because of serialization.

PCIe implements dedicated point to point connections, called lanes, with each device.

A lane is 2 unidirectional pair of 'wires', a pair for transmission in either direction.

PCIe supports tunneling and briding because it exists as part of the conventional PCI protocol, but seldom implemented on consumer systems.

Each PCIe connection is assigned a unique PCI bus ID.

PCIe does support full duplex - able to transmit on both unidirectional signal lanes at same time.

Although serialized, PCIe supports 1 to 32 paralle serial lanes to an end point (device). This provide very high throughput while limiting many problems of a parallel bus.

PCIe implements packetization of all communication, address, data, and control over same data lanes.

A 'data' transfer is packetiezed and serialzed.

Packet information includes is it address, data, control.

RLL encoding is added for clocking. byte->symbol

Complete bytes(symbols) of 'data' are send down a single lane but subsequent bytes are interleaved between avaliable lanes.

Packetization creates additional overhead but allows for much higher transfer speeds, which more than compensate for overhead.

Serialization also allows for greater transfer distances.

Because each device is on a dedicated bus, the controller can interleave communication between the system and more than one bus/device.

Because bits of a byte are serialized on a single lane, bus is less sensitive to skewing. But some synchronization needed on a multi-lane connection.

PCIe uses some form of RLL to provide embedded clock synchronization between the 2 end points but it also provides a separate LVDS clock pair and a special NOP synchronization packet to keep the two end points in sync.

Configuration :

PCI-e 1a :

PCI-e 2 : PCI-e 3 :

Maximum packet size is 4096. bytes.

Packets are multiples of 4 DW (16 byte) units.

Controller an be configured to limit packet size to 128, 256, 512, 1024, or 2048 bytes.

If device being connected only supports smaller packet, that becomes default.

Small block or single byte/word transactions generate a high amount of PCIe is primarily concerned with transmitting packetized information over a serialized connection.

Generally, a PCIe packet has 2 double words (32-bit each) of information for transmitting and addressing the target, (header).

This is follwed by one or more 32-bit words of data up to 4096(-8) or the permitted maximum packet size.

Because PCI supports burst mode, PCIe technically supports it.

overhead. Optimal throughput is only seen when burst transactions occur.