PCI - peripheral component interconnect

Check out : http://www.tech-pro.net/intro_pci.html PCI was designed specifically as an extension bus using protocols independent of the systems local bus.

PCI supports logic based "Plug and Play" configuration.

Detects a device interfaced on the physical bus.
Maps it to a memory bus or I/O bus based system address.
Configures arbitration and interrupts based on information it can obtain from the device..

Configuration :

33 MHz clock. 66 MHz available.
32 bit multiplexed address/data bus width. 64-bit version available.
3 address spaces.
- Memory address space
  Acts as a address decoder for memory mapped I/O
- I/O address space
  Acts as a address decoder for port mapped I/O
- Configuration space. 256 bytes allocated for each device.
  Used by PCI controller to recognize and initialize devices.
FRAME - toggles data lines between address and data.
C/BE - 4-bit command/byte enabled mask, determined by FRAME bit.
4-bit command if FRAME high.
4-bit byte mask if FRAME low.
4 shared interrupt lines.
Independent arbitration lines to each device, GNT#, REQ#.
5 status/control lines, FRAME and IRDY used by initiator, and DEVSEL, TRDY, and STOP used by target.
5 volt signaling. Later reduced to 3.3 volts.
Cards are [usually] notched to prevent voltage miss-match.
Reflected-wave signaling. Limits distance but more power efficient.
Supports 256 buses, 32 devices/bus, 8 functions/device.
Most systems only implement 3 or 4 buses.
But for PCIe, which assigns each device its own bus ID, large value is useful.
Physical implementation of a bus can only have four interface slots.
Physical buses may be daisy chained using bridging logic.
But makes accessing devices more complicated and slower.

CPU neutral - variety of controller chips for interfacing different CPUs to PCI.

Capable of burst data transfers of up to 133MB/s ~ 32 bits * 33 MHz

Implemented with 3 address spaces.

Configuration - used primarily by controller to discover and negotiate connections with devices/expansion cards interfaced with the PCI bus. Configuration memory on device interface could include driver code.
Memory address - provided full memory address range. Devices could claim up to six address ranges. Memory accesses by the CPU or other masters are automatically routed by PCI controller to the appropriate device.
I/O address - (similar to memory bus) primarily for compatibility with original 808x CPU design.

In address mode, 4 bit command/mask lines used to indicate type of transaction being performed.

In data mode, 4 bit command/mask lines used to mask bytes on data lines if not all bytes desired.

Devices may use more than 1 of the 4 interrupts.

Later designed switched to message signaled interrupts. MSI. Initial design provided 32 message interrupts. Later design up this to 2048.

PCI uses a transaction model of data transfer.

Initial configuration negotiations on power-up allocates one or more memory ranges to each device, and DMA and IRQ support, if used.

Once this is done, devices are accessed as memory or I/O mapped address on the system bus.

Any device initiating a data transfer transaction is an initiator.

A device that is targeted for data transfer is the target.

Data is transferred in only one direction during a transaction but it may be either direction.

A initiator places a 4 bit command and the target address on the bus

All targts must latch transaction request and address on 1st clock to free bus for data phase.

Target generally has 5 additional clocks to respond or transaction is aborted.

PCI controller acts as target/interface for actual memory reads/writes.
It also provides DMA logic to address the real memory.

Data transfer begins. If burst mode data transfer supported by initiator and target, the target address is provided only during 1st clock.

It will generate/store successive data transfers.

PCI does not set a limit on the size of the burst transfer, but the sender and receiver most likely does.

Either sender or receiver must terminate burst using the appropriate control and status lines either because of completion but other possible reasons.

Each transaction must be completed or stopped before another transaction can be negotiated and performed.

Both the initiator and the target may stop a burst transaction, either because the transfer is complete or there is a problem. Targets that do not/cannot support burst transactions, treat this as a burst of 1 data transfer. Note that the 133MB/s throughput is based on large block burst transactions.

The PCI configuration space is capable of addressing

256 buses.
Each bus may contain 32 devices.
Each with up to 8 functions.

In practice, when directly connecting to a device on the mother board, each device is assigned its own bus ID.

When access is provide via a set of expansion slots, the number of devices is limited to 4 and assigned to one bus.

Additional slots provide either by a separated bus,
or a bridge with additional slots mapped to another bus ID.

PCI supports arbitration with prioritizationi assignment.

But it also uses a latency register to limit total usage during one mastering session.

For every bus cycle, latency register decremented.

If another master request is detected, controller examines latency register to determine whether to withdraw grant from current master.

Message-singaled interrupts - later versions of PCI (2.2 and up) implemented a messsage based interrupt.
Uses same procedures as data transferal except, transaction indicates it's an interrupt request or clearance.
Allows a device to have 1, 2, 4, 8, 16, or 32 defined interrupts.
With PCI 3.0, this was upped to 2048 interrupts.