ISA (Industrial Standard Architecture) bus
Bus design extended most of the CPU signals and connections to all
devices/circuits.
8-bit (1981, XT)
4.7 MHz
62 pins
20 address pins, 1 MB address range.
8 data pins
Memory Read/Write pins
I/O channel control (2 pins)
Interrupts 2-7 (5), 0 and 1 reserved for CPU
DMA 1,2,3 request and ACK pins (0 reserved for CPU)
I/O channel pin
Power +/-5 volts, +/-12 volts and ground.
Clocks, one for bus and one for refresh(?)
Additional control/status pins
16-bit (1986)
8,10 MHz
32 additional pins
7 additional address pins, 2^27 or 128 MB address range.
8 additional data pins
5 additional interrupts
DMA 0 and 3 more DMA pairs
Additional control/status pins
Signals mostly use single end point signaling. (NOT LPDS)
Requires/uses additional ground trace or other grounding.
Device interaction tightly coupled to a shared clock signal.
Devices were expected to interact at clock speed and at appropriate times
of the clock cycle.
Devices expected to act on a single clock cycle. There is no concept of burst mode.
Signals generally Unipolar encoding - uses a bi-level signal for 0 or 1 where 0 represented by
zero voltage and 1 by a 5 volt level. Generally considered NRZ because there
is no neutral non-bit level.
Because unipolar has a strong DC (power transference) component, seldom
implemented on newer buses.
Some circuitry capable of tri-state electronic decoupling.
Because of clock synchronization and NRZ signalling, there is no other bit/clock
encoding, RLL or otherwise, implemented.
Bus truly passive - provides arbitration and interrupt traces
but arbiter and interrupt logic circuitry not part of protocol.
For devices not able respond at set clock rate but only need a small amount
of additional time, wait signal available.
A wait is a type of hardware "No Operation" during which the bus master
does no work.
Once a wait is cleared, activity resume but always synchronized
to the system clock.
Most common occurrence - CPU accessing primary memory.
For devices requiring longer delays,
Device being accessed latches request.
Device gives up bus access.
Device processes task internally.
Upon completion or trouble,
Device uses interrupts to request master's attention.
Master reestablishes connection at convenient time and finalizes task.
Interrupt (IRQ) signals processed by third party logic circuitry.
IRQ logic receives interrupt from signaling logic.
IRQ logic interrupts CPU.
CPU queries IRQ logic for ID of requesting device.
Handles IRQ request and clears IRQ.
Device interface card provided its own address, DMA, and IRQ recognition
configured using jumpers or switches.
CMOS configuration storage provided additional information to ROM BIOS
calls for handling IRA and DMA requests.
ISA bus does allow multiple master controlled by third party arbiter logic.
The ISA bus does NOT support packeting, task transactions, or messages.
Each clock cycle framed a new interaction between master and target.
Check out : http://www.hardwarebook.info/ISA